"FA" Function in CMOS

CMOS Technology

CMOS technology (Complementary Metal Oxide Semiconductor) offers two types of transistors called "N-channel" and "P-channel". CMOS is currently the dominant technology, at least for digital circuits. Its main advantage with respect to other technologies is a remarkably low power consumption. Indeed the CMOS circuits exhibit a static current (or quiescent current) practically negligible. In the figures below : A logic '1' is represented by the supply voltage Vdd (current values for Vdd are +5V or +3,3V or +2,8V) and is colored in red. A logic '0' is connected to the ground voltage, or GND, is colored in blue. A connection neither to Vdd nor to GND is in yellow. The N-channel transistor conducts when it gate is '1' and the P-channel transistor conducts when its gate is '0' . The keys change the transistor's outline.

CMOS inverter

The CMOS inverter is the most popular gate. It is composed of an N-channel and a P-channel transistors connected through their drain. The figure below illustrates its behavior. The colors conventions are still red for logic '1' and blue for logic '0'. An input voltage in between causes a (mild) short-circuit by maintaining both transistors in conduction. Such a voltage is colored in green. Click on input "a" to pass from '0' to short (green), then to '1', then to short again, then back to '0' and so on. Please notice that when the input is '0' or '1' only one transistor conducts.

Delay and dissipation of the CMOS inverter

We just have seen that the inverter dissipates no energy except during commutation. Indeed if the input is '0' or '1' there is no conduction path between the power supply Vdd and the ground GND. In normal conditions, the short circuit current, (unavoidable during input commutation) lasts a very short time, typically a few picosecondes. The contribution of the parasitic capacitances charge or discharge is much more significant. The transistor gate G forms a capacitance. Anyway this capacitance is necessary to the field effect transistor working. Typically an input capacitance Cg may be around 10 fF. If at time t1, this capacitance is connected to Vdd it is charged (charge Q = Cg * Vdd). If later on, at time t2, the input is connected to GND the capacitance is discharged. This discharge causes a current in the gate I = dQ/dt = (Cg * Vdd)/(t2- t1). Although the gate charge/discharge current is Let us take an example : A modern microprocessor may contain 50 million transistors, meaning about 10 million gates. For each clock cycle, about 1% of those gate commutates. Clock frequency may reach 1 000 MHz (cycle time 1 ns) with a power supply Vdd = 3.3V. The wires connecting the gates most of the time exhibit a parasitic capacitance Cw much larger than the gate input capacitance Cg. Each a wire commutates, all the attached capacitances must be either charged or discharged. : Ctotal=Cg+Cw. An average wire capacitance may be around 1 pF It is rather difficult to estimate the current due to the short-circuits, it is generally small. On the contrary the current due to the commutation activity is important : I = (active gates) * (Ctotal*Vdd) / dt = (1% * 1.000.000) * (1pF * 3.3V) / 2ns = 16 A Finally the quiescent current due to the transistors leaks is quite small (for a conventional circuitry). A static memory SRAM of 2K*8 bits in CMOS let leak 1 µA when not active. The figure below shows the current, or electrons flow in the CMOS inverter. As long as the input stays to '1' or to '0', either the P-channel or the N-channel transistor is blocked and there is no current. When the input changes, the grid of the two transistors must be charged or discharged. This is illustrated by the flow of an electron  (with a negative charge) coming from GND or going to Vss. During the input change, the voltage passes through values that let both transistors conduct, usually during a very short time. This short-circuit current is illustrated by an electron flowing directly from GND to Vss. Finally the output is charged or discharged through the transistors. The output capacitance stores two electrons The power dissipated by a conventional CMOS circuit is consequently directly proportional to the clock frequency.

Electrical simulation of the CMOS inverter

By clicking or dragging the mouse inside the chronogram below, you control the input "a" voltage (plotted in red on the chronogram). The output voltage "y" is then computed (plotted in blue). The current flowing through the N-channel transistor if drawn in green and the current through the P-channel transistor is in yellow. To suspend the applet and freeze the plot, just get the pointer out of the picture.

Basic NOR and NAND gates

We now study some basic CMOS logic gate: a 2-input NOR, a 2-input NAND and finally a full adder cell. Colors conventions: They are the same as the inverter one. Connections to Vdd (logic '1' ) are drawn in red, connections to GND (logic '0' ) are in blue, connections to both Vdd and GND are in green. Finally connections neither to Vdd nor to GND (floating) are in yellow. The two last colors have no logic image. Click close to an input changes its value and consequently the state of the transistors attached to this input. The line in the truth table that corresponds to the input combination is highlighted. Clicking in the truth table changes the input to correspond to the highlighted line. Clicking the top of the table highlight the next line. To simplify the applets, only logical '1' and '0' are allowed for the inputs. Therefore it is not possible to input a value causing a short-circuit between Vdd and GND.

Two-input NOR gate

The two-input nand gate is one of the simplest gates to illustrate the term complementary : the P-channel transistors are connected in serial while the N-channel transistors are in parallel. The P-channel and N-channel network are complementary. Notice that when none of the two P-channel transistors conduct, their common connection is floating (yellow). This is "non logic" value, however, does not cause any trouble since it is not connected to any transistor gate.

The 2-input NAND gate

In the two-input NAND gate, the P-channel transistors are connected in parallel while the two N-channel transistors are in serial.

Complex gates

If the layout at the logic level of a gate demands both symbols "AND" and "OR", this gate is called complex. The generalisation to other compex gates is straightforward. Most of the precaracterised cells libraries actually offer AOI (and-or-inverted), OAI (or-and-inverted), etc..

Binary adder

The "Full Adder" cell ( FA ) is made of two connected complex gates. It realises an arithmetic equality: the weighted sum of the three inputs "x", "y" et "z" is always equal to the weighted sum of the two outputs "c" et "s", in other words " x + y + z = 2*c + s ". This property can easily be checked thanks to the cell truth table. The P-channel transistor network is symmetrical to the N-channel network. A circuit with this property is called "mirror". All the adders exhibit the property that follows from an arithmetic ling between the logic and arithmetic complements. Finally the two circuit outputs are inverted. This derives from an electric property of the CMOS technology, that allows easy design of non-increasing logical functions only