Energy-Efficient Circuit Design Project

 nand2

Download gate netlist and SUE schematic

Data summary:

1) General:
Circuit: nand2
Process: 018tsmc
Setup: Typical-Typical/25°C
Tau= 7.3001e-12 s

2) Logical Effort paramters: f=(g*h+p)
Chart: path:{a>>z} param:{td_r}{td_f}{td_a}
p[td_r]=1.7689 g[td_r]=1.3152
p[td_f]=1.1354 g[td_f]=0.9690
p[td_a]=1.4518 g[td_a]=1.1422
Chart: path:{a>>z} param:{e}
p[e]=1.114e-14 g[e]=1.018e-14
Chart: path:{b>>z} param:{td_r}{td_f}{td_a}
p[td_r]=2.4150 g[td_r]=1.4227
p[td_f]=1.6364 g[td_f]=0.8464
p[td_a]=2.0259 g[td_a]=1.1345
Chart: path:{b>>z} param:{e}
p[e]=1.505e-14 g[e]=1.024e-14

Comparisons of interest:


Charts for the parameter: e
path compared:{a>>z}{b>>z}

Charts for the parameter: td_r
path compared:{a>>z}{b>>z}

Charts for the parameter: td_f
path compared:{a>>z}{b>>z}

Charts for the parameter: td_a
path compared:{a>>z}{b>>z}


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Last updated: 07/22/04.