Energy-Efficient Circuit Design Project

 nor2

Download gate netlist and SUE schematic

Data summary:

1) General:
Circuit: nor2
Process: 018tsmc
Setup: Typical-Typical/25°C
Tau= 7.3001e-12 s

2) Logical Effort paramters: f=(g*h+p)
Chart: path:{a>>z} param:{td_r}{td_f}{td_a}
p[td_r]=1.8201 g[td_r]=1.6861
p[td_f]=1.9686 g[td_f]=1.4267
p[td_a]=1.8920 g[td_a]=1.5570
Chart: path:{a>>z} param:{e}
p[e]=1.148e-14 g[e]=1.285e-14
Chart: path:{b>>z} param:{td_r}{td_f}{td_a}
p[td_r]=2.9805 g[td_r]=1.4712
p[td_f]=2.7716 g[td_f]=1.6946
p[td_a]=2.8757 g[td_a]=1.5830
Chart: path:{b>>z} param:{e}
p[e]=2.153e-14 g[e]=1.23e-14

Comparisons of interest:


Charts for the parameter: e
path compared:{a>>z}{b>>z}

Charts for the parameter: td_r
path compared:{a>>z}{b>>z}

Charts for the parameter: td_f
path compared:{a>>z}{b>>z}

Charts for the parameter: td_a
path compared:{a>>z}{b>>z}


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Last updated: 07/22/04.