//Dual-edge triggered flip-flop model

`timescale 1ns/10ps
`celldefine
module DETFFX1 (Q, QN, D, CK);
output Q, QN;
input  D, CK;
reg NOTIFIER;
supply1 RN, SN;
supply1 dRN, dSN;

  and F0 (rn_and_sn, RN,SN);
  buf     IC (clk, CK);
  udp_detff I0 (n0, D, clk, RN, SN, NOTIFIER);
  and     I4 (flag, RN, SN);
  buf     I1 (Q, n0);
  not     I2 (QN, n0);

  specify
    specparam
    tplh_r$CK$Q   = 1.0,
    tphl_r$CK$Q   = 1.0,
    tplh_r$CK$QN  = 1.0,
    tphl_r$CK$QN  = 1.0,
    tplh_f$CK$Q   = 1.0,
    tphl_f$CK$Q   = 1.0,
    tplh_f$CK$QN  = 1.0,
    tphl_f$CK$QN  = 1.0,
    tsetup_r$D$CK = 1.0,
    tsetup_f$D$CK = 1.0,
    thold_r$D$CK  = 1.0,
    thold_f$D$CK  = 1.0,
    tminpwl$CK    = 1.0,
    tminpwh$CK    = 1.0;
    if (flag)
      (posedge CK *> (Q    +: D)) = (tplh_r$CK$Q,    tphl_r$CK$Q);
    if (flag)
      (posedge CK *> (QN   -: D)) = (tplh_r$CK$QN,   tphl_r$CK$QN);
    if (flag)
      (negedge CK *> (Q    +: D)) = (tplh_f$CK$Q,    tphl_f$CK$Q);
    if (flag)
      (negedge CK *> (QN   -: D)) = (tplh_f$CK$QN,   tphl_f$CK$QN);
    $setuphold(posedge CK &&& (flag == 1), posedge D, tsetup_r$D$CK, thold_r$D$CK, NOTIFIER);
    $setuphold(posedge CK &&& (flag == 1), negedge D, tsetup_r$D$CK, thold_r$D$CK, NOTIFIER);
    $setuphold(posedge CK &&& (flag == 1), posedge D, tsetup_f$D$CK, thold_f$D$CK, NOTIFIER);
    $setuphold(posedge CK &&& (flag == 1), negedge D, tsetup_f$D$CK, thold_f$D$CK, NOTIFIER);
    $width(negedge CK &&& (flag == 1), tminpwl$CK, 0, NOTIFIER);
    $width(posedge CK &&& (flag == 1), tminpwh$CK, 0, NOTIFIER);

   endspecify
endmodule // DETFFX1
`endcelldefine

//
//

primitive udp_detff (out, in, clk, clr_, set_, NOTIFIER);
   output out;
   input  in, clk, clr_, set_, NOTIFIER;
   reg    out;

   table

// in  clk  clr_   set_  NOT  : Qt : Qt+1
//
   0  r   ?   1   ?   : ?  :  0  ; // clock in 0 on rising
   1  r   1   ?   ?   : ?  :  1  ; // clock in 1 on rising
   0  f   ?   1   ?   : ?  :  0  ; // clock in 0 on falling
   1  f   1   ?   ?   : ?  :  1  ; // clock in 1 on falling
   1  *   1   ?   ?   : 1  :  1  ; // reduce pessimism
   0  *   ?   1   ?   : 0  :  0  ; // reduce pessimism
   *  b   ?   ?   ?   : ?  :  -  ; // no changes when in switches
   ?  ?   ?   0   ?   : ?  :  1  ; // set output
   ?  b   1   *   ?   : 1  :  1  ; // cover all transistions on set_
   1  x   1   *   ?   : 1  :  1  ; // cover all transistions on set_
   ?  ?   0   1   ?   : ?  :  0  ; // reset output
   ?  b   *   1   ?   : 0  :  0  ; // cover all transistions on clr_
   0  x   *   1   ?   : 0  :  0  ; // cover all transistions on clr_
   ?  ?   ?   ?   *   : ?  :  x  ; // any notifier changed

   endtable
endprimitive // udp_detff