####################################################################### ########### Timing Report for Single-edge triggered design ############ ####################################################################### ************ Clock Attributes (ns) ****************** **************************************** Report : clocks Design : leon Version: 2003.06-SP1 Date : Fri Apr 23 18:08:14 2004 **************************************** Attributes: d - dont_touch_network f - fix_hold p - propagated_clock G - generated_clock Clock Period Waveform Attrs Sources -------------------------------------------------------------------------------- clk 3.55 {0 1.77305} {clk} -------------------------------------------------------------------------------- **************************************** Report : clock_skew Design : leon Version: 2003.06-SP1 Date : Fri Apr 23 18:08:14 2004 **************************************** Rise Fall Min Rise Min fall Uncertainty Object Delay Delay Delay Delay Plus Minus -------------------------------------------------------------------------------- clk - - - - 0.10 0.10 1 ************ Timing Report (ns) ****************** **************************************** Report : timing -path full -delay max -nworst 2 -max_paths 2 Design : leon Version: 2003.06-SP1 Date : Fri Apr 23 18:08:14 2004 **************************************** # A fanout number of 1000 was used for high fanout net computations. Operating Conditions: typical Library: typical_detff Wire Load Model Mode: segmented Startpoint: mcore0/proc0/rf0/u0_u1 (rising edge-triggered flip-flop clocked by clk') Endpoint: mcore0/proc0/iu0/ex_reg_RS2DATA__11_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ generic_clkgen TSMC18_Conservative typical_detff clkgen TSMC18_Conservative typical_detff regfile_iu_rftype1_abits8_dbits32_words136 TSMC18_Conservative typical_detff proc TSMC18_Conservative typical_detff leon TSMC18_Conservative typical_detff mcore TSMC18_Conservative typical_detff iu TSMC18_Conservative typical_detff Point Incr Path -------------------------------------------------------------------------- clock clk' (rise edge) 1.77 1.77 clock network delay (ideal) 0.00 1.77 mcore0/proc0/rf0/u0_u1/CLKB (dpram136x32) 0.00 1.77 r mcore0/proc0/rf0/u0_u1/QB[11] (dpram136x32) 1.27 3.05 f mcore0/proc0/rf0/rfo[11] (regfile_iu_rftype1_abits8_dbits32_words136) 0.00 3.05 f mcore0/proc0/iu0/rfo[11] (iu) 0.00 3.05 f mcore0/proc0/iu0/U32455/Y (INVX8) 0.03 3.08 r mcore0/proc0/iu0/U31297/Y (OAI21X4) 0.04 3.12 f mcore0/proc0/iu0/U29903/Y (NOR3BX4) 0.11 3.23 r mcore0/proc0/iu0/U30112/Y (OAI2BB1X4) 0.03 3.26 f mcore0/proc0/iu0/U29901/Y (NAND2X2) 0.05 3.31 r mcore0/proc0/iu0/U29902/Y (INVX1) 0.03 3.34 f mcore0/proc0/iu0/ex_reg_RS2DATA__11_/D (DFFX1) 0.00 3.34 f data arrival time 3.34 clock clk (rise edge) 3.55 3.55 clock network delay (ideal) 0.00 3.55 clock uncertainty -0.10 3.45 mcore0/proc0/iu0/ex_reg_RS2DATA__11_/CK (DFFX1) 0.00 3.45 r library setup time -0.10 3.34 data required time 3.34 -------------------------------------------------------------------------- data required time 3.34 data arrival time -3.34 -------------------------------------------------------------------------- slack (MET) 0.00 Startpoint: mcore0/proc0/rf0/u0_u1 (rising edge-triggered flip-flop clocked by clk') Endpoint: mcore0/proc0/iu0/ex_reg_RS2DATA__5_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ generic_clkgen TSMC18_Conservative typical_detff clkgen TSMC18_Conservative typical_detff regfile_iu_rftype1_abits8_dbits32_words136 TSMC18_Conservative typical_detff proc TSMC18_Conservative typical_detff leon TSMC18_Conservative typical_detff mcore TSMC18_Conservative typical_detff iu TSMC18_Conservative typical_detff Point Incr Path -------------------------------------------------------------------------- clock clk' (rise edge) 1.77 1.77 clock network delay (ideal) 0.00 1.77 mcore0/proc0/rf0/u0_u1/CLKB (dpram136x32) 0.00 1.77 r mcore0/proc0/rf0/u0_u1/QB[5] (dpram136x32) 1.27 3.05 f mcore0/proc0/rf0/rfo[5] (regfile_iu_rftype1_abits8_dbits32_words136) 0.00 3.05 f mcore0/proc0/iu0/rfo[5] (iu) 0.00 3.05 f mcore0/proc0/iu0/U32475/Y (INVX8) 0.03 3.08 r mcore0/proc0/iu0/U31196/Y (OAI21X4) 0.04 3.12 f mcore0/proc0/iu0/U29928/Y (NOR3X4) 0.12 3.24 r mcore0/proc0/iu0/U30117/Y (OAI2BB1X4) 0.03 3.27 f mcore0/proc0/iu0/U29927/Y (INVX4) 0.03 3.31 r mcore0/proc0/iu0/U29926/Y (AOI21X1) 0.04 3.34 f mcore0/proc0/iu0/ex_reg_RS2DATA__5_/D (DFFX1) 0.00 3.34 f data arrival time 3.34 clock clk (rise edge) 3.55 3.55 clock network delay (ideal) 0.00 3.55 clock uncertainty -0.10 3.45 mcore0/proc0/iu0/ex_reg_RS2DATA__5_/CK (DFFX1) 0.00 3.45 r library setup time -0.10 3.34 data required time 3.34 -------------------------------------------------------------------------- data required time 3.34 data arrival time -3.34 -------------------------------------------------------------------------- slack (MET) 0.00 Startpoint: mcore0/amod0/mctrl0_r_reg_ADDRESS__0_ (rising edge-triggered flip-flop clocked by clk) Endpoint: address[0] (output port) Path Group: default Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ clkgen TSMC18_Conservative typical_detff amod TSMC18_Conservative typical_detff leon TSMC18_Conservative typical_detff mcore TSMC18_Conservative typical_detff generic_clkgen TSMC18_Conservative typical_detff regfile_iu_rftype1_abits8_dbits32_words136 TSMC18_Conservative typical_detff cachemem TSMC18_Conservative typical_detff cache TSMC18_Conservative typical_detff iu TSMC18_Conservative typical_detff proc TSMC18_Conservative typical_detff Point Incr Path -------------------------------------------------------------------------- mcore0/amod0/mctrl0_r_reg_ADDRESS__0_/CK (DFFX1) 0.00 # 0.00 r mcore0/amod0/mctrl0_r_reg_ADDRESS__0_/Q (DFFX1) 0.93 0.93 r mcore0/amod0/memo[56] (amod) 0.00 0.93 r mcore0/memo[56] (mcore) 0.00 0.93 r U33/PAD (PRT08DGZ) 1.05 1.98 r address[0] (out) 0.00 1.98 r data arrival time 1.98 max_delay 4.00 4.00 output external delay 0.00 4.00 data required time 4.00 -------------------------------------------------------------------------- data required time 4.00 data arrival time -1.98 -------------------------------------------------------------------------- slack (MET) 2.02 Startpoint: mcore0/amod0/mctrl0_r_reg_READ_ (rising edge-triggered flip-flop clocked by clk) Endpoint: read (output port) Path Group: default Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ clkgen TSMC18_Conservative typical_detff amod TSMC18_Conservative typical_detff leon TSMC18_Conservative typical_detff mcore TSMC18_Conservative typical_detff generic_clkgen TSMC18_Conservative typical_detff regfile_iu_rftype1_abits8_dbits32_words136 TSMC18_Conservative typical_detff cachemem TSMC18_Conservative typical_detff cache TSMC18_Conservative typical_detff iu TSMC18_Conservative typical_detff proc TSMC18_Conservative typical_detff Point Incr Path -------------------------------------------------------------------------- mcore0/amod0/mctrl0_r_reg_READ_/CK (DFFX1) 0.00 # 0.00 r mcore0/amod0/mctrl0_r_reg_READ_/Q (DFFX1) 0.74 0.74 r mcore0/amod0/memo[0] (amod) 0.00 0.74 r mcore0/memo[0] (mcore) 0.00 0.74 r U84/PAD (PDT04DGZ) 1.08 1.82 r read (out) 0.00 1.82 r data arrival time 1.82 max_delay 4.00 4.00 output external delay 0.00 4.00 data required time 4.00 -------------------------------------------------------------------------- data required time 4.00 data arrival time -1.82 -------------------------------------------------------------------------- slack (MET) 2.18 1