####################################################################### ################ Timing Report for SPGFF design ###################### ####################################################################### ***************************************** Clock Attributes (ns) ********************** Information: Updating design information... (UID-85) Warning: Design 'leon' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) **************************************** Report : clocks Design : leon Version: 2003.06-SP1 Date : Fri Apr 23 18:34:22 2004 **************************************** Attributes: d - dont_touch_network f - fix_hold p - propagated_clock G - generated_clock Clock Period Waveform Attrs Sources -------------------------------------------------------------------------------- clk 3.24 {0 1.61812} {clk} -------------------------------------------------------------------------------- **************************************** Report : clock_skew Design : leon Version: 2003.06-SP1 Date : Fri Apr 23 18:34:22 2004 **************************************** Rise Fall Min Rise Min fall Uncertainty Object Delay Delay Delay Delay Plus Minus -------------------------------------------------------------------------------- clk - - - - 0.10 0.10 1 *************************************** Timing Report (ns) ********************** **************************************** Report : timing -path full -delay max -nworst 2 -max_paths 2 Design : leon Version: 2003.06-SP1 Date : Fri Apr 23 18:34:22 2004 **************************************** # A fanout number of 1000 was used for high fanout net computations. Operating Conditions: typical Library: typical_detff Wire Load Model Mode: segmented Startpoint: mcore0/proc0/rf0/u0_u1 (rising edge-triggered flip-flop clocked by clk') Endpoint: mcore0/proc0/iu0/ex_reg_RS2DATA__25_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ generic_clkgen TSMC18_Conservative typical_detff clkgen TSMC18_Conservative typical_detff regfile_iu_rftype1_abits8_dbits32_words136 TSMC18_Conservative typical_detff proc TSMC18_Conservative typical_detff leon TSMC18_Conservative typical_detff mcore TSMC18_Conservative typical_detff iu TSMC18_Conservative typical_detff Point Incr Path -------------------------------------------------------------------------- clock clk' (rise edge) 1.62 1.62 clock network delay (ideal) 0.00 1.62 mcore0/proc0/rf0/u0_u1/CLKB (dpram136x32) 0.00 1.62 r mcore0/proc0/rf0/u0_u1/QB[25] (dpram136x32) 1.28 2.90 r mcore0/proc0/rf0/rfo[25] (regfile_iu_rftype1_abits8_dbits32_words136) 0.00 2.90 r mcore0/proc0/iu0/rfo[25] (iu) 0.00 2.90 r mcore0/proc0/iu0/U32419/Y (INVX8) 0.02 2.92 f mcore0/proc0/iu0/U31087/Y (OAI21X4) 0.09 3.01 r mcore0/proc0/iu0/U31089/Y (NOR2X4) 0.03 3.04 f mcore0/proc0/iu0/U30206/Y (OAI21X4) 0.04 3.08 r mcore0/proc0/iu0/U32677/Y (AND2X1) 0.12 3.20 r mcore0/proc0/iu0/ex_reg_RS2DATA__25_/D (SPGFFX1) 0.00 3.20 r data arrival time 3.20 clock clk (rise edge) 3.24 3.24 clock network delay (ideal) 0.00 3.24 clock uncertainty -0.10 3.14 mcore0/proc0/iu0/ex_reg_RS2DATA__25_/CK (SPGFFX1) 0.00 3.14 r library setup time 0.07 3.20 data required time 3.20 -------------------------------------------------------------------------- data required time 3.20 data arrival time -3.20 -------------------------------------------------------------------------- slack (MET) 0.00 Startpoint: mcore0/proc0/rf0/u0_u1 (rising edge-triggered flip-flop clocked by clk') Endpoint: mcore0/proc0/iu0/ex_reg_RS2DATA__2_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ generic_clkgen TSMC18_Conservative typical_detff clkgen TSMC18_Conservative typical_detff regfile_iu_rftype1_abits8_dbits32_words136 TSMC18_Conservative typical_detff proc TSMC18_Conservative typical_detff leon TSMC18_Conservative typical_detff mcore TSMC18_Conservative typical_detff iu TSMC18_Conservative typical_detff Point Incr Path -------------------------------------------------------------------------- clock clk' (rise edge) 1.62 1.62 clock network delay (ideal) 0.00 1.62 mcore0/proc0/rf0/u0_u1/CLKB (dpram136x32) 0.00 1.62 r mcore0/proc0/rf0/u0_u1/QB[2] (dpram136x32) 1.28 2.90 r mcore0/proc0/rf0/rfo[2] (regfile_iu_rftype1_abits8_dbits32_words136) 0.00 2.90 r mcore0/proc0/iu0/rfo[2] (iu) 0.00 2.90 r mcore0/proc0/iu0/U29819/Y (INVX8) 0.02 2.92 f mcore0/proc0/iu0/U31063/Y (OAI21X4) 0.09 3.01 r mcore0/proc0/iu0/U31066/Y (NOR2X4) 0.03 3.04 f mcore0/proc0/iu0/U30178/Y (OAI21X4) 0.04 3.08 r mcore0/proc0/iu0/U32691/Y (AND2X1) 0.12 3.20 r mcore0/proc0/iu0/ex_reg_RS2DATA__2_/D (SPGFFX1) 0.00 3.20 r data arrival time 3.20 clock clk (rise edge) 3.24 3.24 clock network delay (ideal) 0.00 3.24 clock uncertainty -0.10 3.14 mcore0/proc0/iu0/ex_reg_RS2DATA__2_/CK (SPGFFX1) 0.00 3.14 r library setup time 0.07 3.20 data required time 3.20 -------------------------------------------------------------------------- data required time 3.20 data arrival time -3.20 -------------------------------------------------------------------------- slack (MET) 0.00 Startpoint: mcore0/amod0/mctrl0_r_reg_RAMSN__0_ (rising edge-triggered flip-flop clocked by clk) Endpoint: ramsn[0] (output port) Path Group: default Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ clkgen TSMC18_Conservative typical_detff amod TSMC18_Conservative typical_detff leon TSMC18_Conservative typical_detff mcore TSMC18_Conservative typical_detff generic_clkgen TSMC18_Conservative typical_detff regfile_iu_rftype1_abits8_dbits32_words136 TSMC18_Conservative typical_detff cachemem TSMC18_Conservative typical_detff cache TSMC18_Conservative typical_detff iu TSMC18_Conservative typical_detff proc TSMC18_Conservative typical_detff Point Incr Path -------------------------------------------------------------------------- mcore0/amod0/mctrl0_r_reg_RAMSN__0_/CK (DFFSRX1) 0.00 # 0.00 r mcore0/amod0/mctrl0_r_reg_RAMSN__0_/Q (DFFSRX1) 1.08 1.08 r mcore0/amod0/memo[19] (amod) 0.00 1.08 r mcore0/memo[19] (mcore) 0.00 1.08 r U70/PAD (PDT04DGZ) 1.13 2.21 r ramsn[0] (out) 0.00 2.21 r data arrival time 2.21 max_delay 4.00 4.00 output external delay 0.00 4.00 data required time 4.00 -------------------------------------------------------------------------- data required time 4.00 data arrival time -2.21 -------------------------------------------------------------------------- slack (MET) 1.79 Startpoint: mcore0/amod0/mctrl0_r_reg_RAMSN__1_ (rising edge-triggered flip-flop clocked by clk) Endpoint: ramsn[1] (output port) Path Group: default Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ clkgen TSMC18_Conservative typical_detff amod TSMC18_Conservative typical_detff leon TSMC18_Conservative typical_detff mcore TSMC18_Conservative typical_detff generic_clkgen TSMC18_Conservative typical_detff regfile_iu_rftype1_abits8_dbits32_words136 TSMC18_Conservative typical_detff cachemem TSMC18_Conservative typical_detff cache TSMC18_Conservative typical_detff iu TSMC18_Conservative typical_detff proc TSMC18_Conservative typical_detff Point Incr Path -------------------------------------------------------------------------- mcore0/amod0/mctrl0_r_reg_RAMSN__1_/CK (DFFSRX1) 0.00 # 0.00 r mcore0/amod0/mctrl0_r_reg_RAMSN__1_/Q (DFFSRX1) 1.08 1.08 r mcore0/amod0/memo[20] (amod) 0.00 1.08 r mcore0/memo[20] (mcore) 0.00 1.08 r U69/PAD (PDT04DGZ) 1.13 2.21 r ramsn[1] (out) 0.00 2.21 r data arrival time 2.21 max_delay 4.00 4.00 output external delay 0.00 4.00 data required time 4.00 -------------------------------------------------------------------------- data required time 4.00 data arrival time -2.21 -------------------------------------------------------------------------- slack (MET) 1.79 1