Short-Circuit Energy Component

 

     Short-Circuit current on the direct path from power supply Vdd to the ground exists while p-MOS and n-MOS transistors are both conducting. This is the case during the output switching time, both charging and discharging. 
Consequently, energy dissipation due to the short-circuit energy component is calculated by multiplying the energy of one transition with the output switching activity factor.
       Energy associated with short-circuit component can be measured by integrating the current of the n-mos transistor during the low-to-high output transition, and vice versa by measuring the p-mos current while the n-mos is discharging the output to low value. The current due to the capacitive coupling is isolated and taken into account as well.
       The first solution of the short-circuit energy component dissipated in the inverted was given by [Veendrick 84]. More accurate model was presented by [Hedenstierna and Jeppson 87]. Both models were based on the square-low MOS equations. [Sakurai and Newton 90] introduced alpha-power law MOS model and derived expression for short-circuit energy dissipation of the inverter under the same assumptions as in [Veendrick 84].

        Design considerations for minimizing the short-circuit energy component are given in the following examples.

Verba docent, exampla trahunt

    
In order to illustrate the effect of input/output transition times, i.e. input/output slopes, and output load on the short-circuit energy dissipation of the inverter gate under test, the setup shown in Figure 1 is used.

 

 

Figure 1. Circuit setup

 

By varying output and input fanouts, h and q, respectively, the measured short-circuit energy component is illustrated in Figure 2.
The maximum of the short-circuit energy dissipation occurs when the input fanout is big (q), whereas the fanout at the output is small (h).

 

Figure 2. Short-Circuit Energy dependence on input/output fanouts (q and h, respectively)
 

With a certain amount of latitude remaining, the rule for minimization of associated short-circuit energy component would be right-hand side of the polyhedron. The concluding remarks of the analysis given in [Veendrick 84] state that if the output and input signal have equal transition times, the short-circuit will be only a fraction (<20%) of the total dissipation and to minimize the short-circuit energy dissipation an inverter should be designed in a way that the input transition times are less than or about equal to the output transition times.
The proposed optimization corresponds to the setup case shown in Figure 1 and having  the equal slopes at  the input and output when q value is set to be equal to h. The results are summarized in the following graphs, Figures 3, 4.

 

 

 
 

Figure 3. Short-Circuit Energy Dissipation for equal input/output fanouts (h=q)

 

Figure 4. Percentage of Esc in total energy dissipation, Etot, versus h (h=q).

 

References:


[Al-Khalili et. al. 90] A. J. Al-Khalili, Y. Zhu, D. Al-Khalili, "A Module Generator for Optimized CMOS Buffers", IEEE Transactions on Computer-Aided Design and Integrated Circuits and Systems, Vol. 9, No. 10, October 1990.
[Hedenstierna and Jeppson 87] N. Hedenstierna, K. O. Jeppson, "CMOS Circuit Speed and Buffer Optimization", IEEE Transactions on Computer-Aided Design, CAD-6(2), pp. 270-281, 1987.
[Hedenstierna and Jeppson 93] N. Hedenstierna, K. O. Jeppson, "Comments on 'A Module Generator for Optimized CMOS Buffers'", IEEE Transactions on Computer-Aided Design of Integrated CIrcuits and Systems, Vol. 12, January 1993.

[Kang 1986] S. M. Kang, "Accurate Simulation of Power Dissipation in VLSI Circuits", IEEE Journal of Solid-State Circuits, Vol. 21, No. 5, pp. 889-891, October 1986.
[Nose and Sakurai 00] K. Nose, T. Sakurai, "Analysis and Future Trend of Short-Circuit Power", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 9, September 2000.
[Sakurai and Newton 90] T. Sakurai, A. R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas", IEEE Journal of Solid-State Circuits, 25(2), pp. 584-594.
[Turgis et. al. 95] S. Turgis, N. Azemard, D. Auvergne, "Explicit Evaluation of Short Circiut Power Dissipation for CMOS Logic Structures", ISLPED 1995.
[Veendrick 84] H. J. M. Veendrick, "Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits", IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 468-473, August 1984.
[Yacoub and Ku 89] G. Y. Yacoub, W. H. Ku, "An Enchanced Technique for Simulating Short-Circuit Power Dissipation", IEEE Journal of Solid-State Circuits, June 1989.