14^th IEEE Symposium on Computer Arithmetic

April 14-16, 1999
Adelaide, Australia

General Chair: Jean-Michel Muller
Program Co-Chairs: Israel Koren and Peter Kornerup


[contents]

Preface

Conference Website: http://www.ecs.umass.edu/ece/arith14/

Israel Koren, Peter Kornerup, "Fourteenth IEEE Symposium on Computer Arithmetic: Foreword"

Invited Talk - Israel Koren, Chairman

R. P. Brent, "Computer Arithmetic - A Programmer's Perspective"

Section 1: Processor Enhancements - Peter Kornerup, Chairman

S. Story, Ping Tak Peter Tang, "New Algorithms for Improved Transcendental Functions on IA-64"

M. S. Schmookler, M. Putrino, C. Roth, M. Sharma, A. Mather, J. Tyler, H. Van Nguyen, M. N. Pham, J. Lent, "A Low-Power, High-Speed IARITH14_on of a PowerPC^TM Microprocessor Vector Extension"

Section 2: Addition - Neil Weste, Chairman

D. S. Phatak, I. Koren, "Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition"

S. Knowles, "A Family of Adders"

A. Beaumont-Smith, N. Burgess, S. Lefrere, C. C. Lim, "Reduced Latency IEEE Floating-Point Standard Adder Architectures"

Section 3: Division - Renato Stefanelli, Chairman

A. F. Tenca, M. D. Ercegovac, "On the Design of High-Radix On-line Division for Long Precision"

P. Montuschi, T. Lang, "Boosting Very-High Radix Division with Prescaling and Selection by Rounding"

A. Nannarelli, T. Lang, "Low-Power Division: Comparison among Implementations of Radix-4, 8, and 16"

Section 4: Cryptography and Graphics - Milos Ercegovac, Chairman

T. Blum, C. Paar, "Montgomery Modular Exponentiation on Reconfigurable Hardware"

C. D. Walter, "Moduli for Testing Implementations of the RSA Cryptosystem"

N. Takagi, S. Kuwahara, "Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector"

Section 5: Divide and Square Root - Atsuki Inoue, Chairman

M. A. Cornea-Hasegan, R. A. Golliver, P. Markstein, "Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms"

S. F. Oberman, "Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7^TM Microprocessor"

R. C. Agarwal, F. G. Gustavson, M. S. Schmookler, "Series Approximation Methods for Divide and Square Root in the Power3^TM Processor"

M. J. Schulte, K. E. Wires, "High-Speed Inverse Square Roots"

Section 6: Number Systems - Colin Walter, Chairman

A. Saed, M. Ahmadi, G. A. Jullien, "Arithmetic with Signed Analog Digits"

J. N. Coleman, E. I. Chester, "A 32-bit Logarithmic Arithmetic Unit and Its Performance Compared to Floating-Point"

P. Kornerup, "Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition"

Section 7: Residue Number Systems - Graham Jullien, Chairman

R. Zimmermann, "Efficient VLSI Implementation of modulo (2ⁿ±1) Addition and Multiplication"

M. Bhardwaj, T. Srikanthan, C. T. Clark, "A Reverse Converter for the 4-moduli Superset {2ⁿ-1, 2 ⁿ, 2ⁿ+1, 2ⁿ⁺¹+1}"

M. Bhardwaj, T. Srikanthan, C. T. Clark, "VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspective"

Section 8: CORDIC Algorithms - Jeong Lee, Chairman

J. Hormigo, J. Villalba, E. L. Zapata, "Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm"

D. Lewis, "Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms"

E. Antelo, T. Lang, J. D. Bruguera, "Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding"

Section 9: Multiplication and Rounding - William McAllister, Chairman

J.-J. J. Lue, D. S. Phatak,  "Area x  Delay ( A·T )  Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation"

G. Even, P. -M. Seidel, "A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication"

C. Iordache, D. W. Matula, "On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal"

M. Parks, "Number-Theoretic Test Generation for Directed Rounding"

Section 10: Floating Point - Stuart F. Oberman, Chairman

M. Daumas, "Multiplications of Floating Point Expansions"

E. M. Schwarz, R. M. Smith, C. A. Krygowski, "The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures"

G. Gerwig, M. Kroener, "Floating-Point Unit in Standard Cell Design with 116-bit Wide Dataflow"