15th IEEE Symposium on Computer Arithmetic
June 11-13, 2001
General Chair: David Matula
Program Co-Chairs: Neil Burgess and Luigi Ciminiera
Neil Burgess, Luigi Ciminiera, "Fiftheenth IEEE Symposium on Computer Arithmetic: Foreword"
Keynote Speech - Neil Burgess, Chairman
Ruby B. Lee, "Computer Arithmetic - A Processor Architect's Perspective"
Section 1: Binary Strings in Computer Arithmetic - Luigi Ciminiera, Chairman
M. S. Schmookler, K. J. Nowka, "Leading Zero Anticipation and Detection - A Comparison of Methods"
T. Lang, J. -M. Muller, "Bounds on Runs of Zeros and Ones for Algebraic Functions"
Section 2: Multiplication and Exponentiation - Vojin G. Oklobdzija, Chairman
P. -M. Seidel, L. D. McFearin, D. W. Matula, "Binary Multiplication Radix-32 and Radix-256"
K. C. Bickerstaff, E. E. Swartzlander Jr. M. J. Schulte, "Analysis of Column Compression Multipliers"
J. A. Pineiro, J. D. Bruguera, J. M. Muller, "Faithful Powering Computation Using Table Look-up and a Fused Accumulation Tree"
Section 3: Cryptography - Luigi Dadda, Chairman
Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee, "Bit-Parallel Systolic Modular Multipliers for a Class of GF (2m )"
J. -C. Bajard, L. -S. Didier, P. Kornerup, "Modular Multiplication and Base Extensions in Residue Number Systems"
M. A. Hasan, "Efficient Computation of Multiplicative Inverses for Cryptographic Applications"
B. Phillips, "Optimized Squaring of Long Integers Using Precomputed Partial Products"
Section 4: Division and Square Root - Mike Schulte, Chairman
T. Lang, E. Antelo, "Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation"
N. Takagi, "A Hardware Algorithm for Computing Reciprocal Square Root"
D. W. Matula, "Improved Table Look-up Algorithms for Postscaled Division"
Section 5: Elementary Functions and Rounding - Paolo Montuschi, Chairman
V. Lefevre, J. -M. Muller, "Worst Cases for Correct Rounding of the Elementary Functions in Double Precision"
L. D. McFearin, D. W. Matula, "Generation and Analysis of Hard to Round Cases for Binary Floating Point Division"
F. de Dinechin, A. Tisserand, "Some Improvements on Multipartite Table Methods"
J. Cao, B. W. Y. Wei, J. Cheng, "High-Performance Architectures for Elementary Function Generation"
Section 6: Number Systems - Peter Kornerup, Chairman
M. F. Cowlishaw, E. M. Schwarz, R. M. Smith, C. F. Webb, "A Decimal Floating-Point Specification"
Y. Hida, X. S. Li, D. H. Bailey, "Algorithms for Quad-Double Precision Floating Point Arithmetic"
D. Lester, "Effective Continued Fractions"
Section 7: Floating Point Units - David Hough, Chairman
A. Naini, A. Dhablania, W. James, D. Das Sarma, "1 GHz HAL SPARC64R Dual Floating Point Unit with RAS Features"
P. -M. Seidel, G. Even, "On the Design of Fast IEEE Floating-Point Adders"
Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Sang-Woo Kim, Moon-Key Lee, "In Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32"
Section 8: Addition - Simon Knowles, Chairman
J. D. Bruguera, T. Lang, "Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition"
H. T. Vergos, C. Efstathiou, D. Nikolos, "High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operends"
A. Beaumont-Smith, C. -C. Lim, "Parallel Prefix Adder Design"
Section 9: Logarithmic Number Systems - Renato Stefanelli, Chairman
V. Paliouras, T. Stouraitis, "Low-Power Properties of the Logarithmic Number System"
M. G. Arnold, C. Walter, "Unrestricted Faithful Rounding is Good Enough for Some LNS Applications"
V. S. Dimitrov, J. Eskritt, L. Imbert, G. A. Jullien, W. C. Miller, "The Use of the Multi-Dimensional Logarithmic Number System in DSP"
Section 10: On-Line Arithmetic - Milos Ercegovac, Chairman
S. Rajagopal, J. R. Cavallaro, "On-line Arithmetic for Detection in Digital Communication Receivers"
A. F. Tenca, S. U. Hussaini, "A Design of Radix-2 On-line Division using LSA Organization"
Addendum: Reprinted Paper from the 14th Computer Arithmetic Symposium - Luigi Ciminiera, Chairman
S. Knowles, "A Family of Adders"