5th IEEE Symposium on Computer Arithmetic
May 18-19, 1981
University of Michigan, Ann Arbor, Michigan
General Chair: Daniel E. Atkins
Program Co-Chair: Kishor S. Trivedi
D. E. Atkins, K. S. Trivedi, "The Fifth IEEE Symposium on Computer Arithmetic: Foreword"
Session 1: Non-Traditional Number SystemsT. R. N. Rao, "Arithmetic of Finite Fields"
P. Ligomenides and R. Newcomb, "Complement Representations in the Fibonacci Computer"
T. M. Rao and R. T. Gregory, "The Conversion of Hensel Codes to Rational Numbers"
S. Ong and D. E. Atkins, "Towards Quantitative Comparison of Computer Number Systems"
Session 2: Design and Implementation of Arithmetic ProcessorsJ. E. Robertson, "A Systematic Approach to the Design of Structures for Arithmetic"
D. D. Nguyen, "A Systematic Approach to the Design of Structures for Addition and Subtraction -- Case of Radix r = mk"
J. B. Gosling, J. H. P. Zurawski and D. B. G. Edwards, "A Chip-Set for a High-Speed Low-Cost Floating - Point Unit"
C. L. Bridge, P. D. Fisher and R. G. Reynolds, "Asynchronous Arithmetic Algorithms for Data-Driven Machines"
Session 3: On - Line Arithmetic
R. M. Owens, "Compound Algorithms for Digit On - Line Arithmetic"
A. Gorji-Sinaki and M. D. Ercegovac, "Design of a Digit - Slice On - Line Arithmetic Unit"
O. Watanuki and M. D. Ercegovac, "Floating - Point On - Line Arithmetic: Algorithms"
O. Watanuki and M. D. Ercegovac, "Floating - Point On - Line Arithmetic: Error Analysis"
C. S. Raghavendra and M. D. Ercegovac, "A Simulator for On - Line Arithmetic"
Session 4: Error Control and Error AnalysisJ. Barlow, "On the Distribution of Accumulated Roundoff Error in Floating Point Arithmetic"
M. Cohen, V. C. Hamacher and T. E. Hull, "CADAC: An Arithmetic Unit for Clean Decimal Arithmetic and Controlled Precision"
J. Demmel, "Effects of Underflow on Solving Linear Systems"
Session 5: Function EvaluationH. Peng, "Algorithms for Extracting Square Roots and Cube Roots"
G. S. Taylor, "Compatible Hardware for Division and Square Root"
R. Willoner and I - N. Chen, "An Algorithm for Modular Exponentiation"
P. M. Farmwald, "High Bandwidth Evaluation of Elementary Functions"
Session 6: Residue Arithmetic and CodesR. T. Gregory, "Residue Arithmetic with Rational Operands"
S. Kaushik and R. K. Arora, "Sign Detection in the Symmetric Residue Number System"
R. K. Arora and S. Kaushik, "Conversion Scheme in Residue Code"
D. K. Banerji, T - Y. Cheung and V. Ganesan, "A High-Speed Division Method in Residue Arithmetic"
A. Avizienis, "Low - Cost Residue and Inverse Residue Error - Detecting Codes for Signed - Digit Arithmetic"
Session 7: Case Studies SessionD. F. Davis, "Elementary Functions on an Array Processor"
G. Walker, "Extension of the MC68000 Architecture to Include Standard Floating - Point Arithmetic"
R. A. Rutenbar and Y. E. Park, "Case Study of a VLSI Design Project: A Simple Inner Product Machine"
G. S. Taylor and D. A. Patterson, "Vax Hardware for the Proposed IEEE Floating - Point Standard"
Session 8: Special Purpose ProcessorsP. Chow, Z. G. Vranesic and J. L. Yen, "A Pipelined Distributed Arithmetic PFFT Processor"
L. Ciminiera and A. Serra, "Arithmetic Array for Fast Inner Product Evaluation"
L. Ciminiera, A Serra and A. Valenzano, "Fast and Accurate Matrix Triangularization Using an Iterative Structure"
K. Hwang and Y - H. Cheng, "Partitioned Algorithms and VLSI Structures for Large - Scale Matrix Computations"
P. Kornerup and D. W. Matula, "An Integrated Rational Arithmetic Unit"
M. J. Irwin and D. R. Smith, "A Rational Arithmetic Processor"
Session 9: Schemes for Addition and MultiplicationH. Kobayashi, "A Fast Multi-Operand Multiplication Scheme"
K. Efe, "Multi-Operand Addition with Conditional Sum Logic"
C. A. Papachristou, "Algorithms for Parallel Addition and Parallel Polynomial Evaluation"
L. Bhuyan and D. P. Agrawal, "Multiple Addition and Parallel Counter in Generalized Binary and Negabinary Systems"
D. P. Agrawal and R. C. Joshi, "Negabinary Addition and Multiplication Using Binary Circuits"
Late PaperS. Markov, "On an Interval Arithmetic and Its Applications"