6th IEEE Symposium on Computer Arithmetic

June 20-22, 1983
 Aarhus University, Aarhus, Denmark

General Chair: T. R. N. Rao
Program Co-Chair: Peter Kornerup


[contents]

Preface

T. R. N. Rao and P. Kornerup, "The Sixth IEEE Symposium on Computer Arithmetic: Foreword"

Session 1: VLSI

J. Ferguson and J. P. Shen, "The Design of Two Easily-Testable VLSI Array Multipliers"

S. Ong and D. E. Atkins, "A Comparison of ALU Structures for VLSI Technology"

D. P. Agrawal, G. C. Pathak, N. K. Swain and B. K. Agrawal, "On Design and Performance of VLSI Based Parallel Multiplier"

L. Guibas and J. Vuillemin, "On Fast Binary Addition in MOS Technologies"

Session 2: Number Systems & Residue Arithmetic

S. Kaushik, "Sign Detection in Non-Redundant Residue Number Systems with Reduced Information"

D. K. Banerji and S. Kaushik, "Representation and Processing of Fractions in a Residue System"
A. S. Fraenkel, "Systems of Numeration"

Session 3: Multiplication

M. Annaratone and R. Stefanelli, "A Multiplier with Multiple Error Correction Capability"

L. Dadda, "Some Schemes for Fast Serial Input Multipliers"

L. Ciminiera and A. Serra, "Fast Iterative Multiplying Array"

J. E. Robertson, "Conditions for the Distributivity of Multiplication with Respect to Set Addition and Their Effect on the Design of Array Multipliers"

Session 4: Numerical Error Control

R. Morrison, A. J. Cole, P. J. Bailey, M. A. Wolfe and M. Shearer, "Experience with a High Level Language that Supports Interval Arithmetic"

P. J. L. Wallis, "ADA Floating-Point Arithmetic as a Basis for Portable Numerical Software"

S. Markov, "On the Numerical Algorithm Formulated in Computer Arithmetic"

W. S. Brown and C. S. Wetherell, "A Numeric Error Algebra"

Session 5: Algorithms & Implementation

M. D. Ercegovac, "A Higher-Radix Division with Simple Selection of Quotient Digits"

S. Majerski, "Square-Root Algorithms for High-Speed Digital Circuits"

J. B. Gosling, "Some Tricks of the (Floating-Point) Trade"

R. V. Donthi, M. Saleem and H. Singh, "On Bit Sequential Multipliers"

Session 6: Case Studies

G. S. Taylor, "Arithmetic on the ELXSI System 6400"

L. Ohlsson and B. Svensson, "Matrix Multiplication on LUCAS"

I. Scherson and S. Ruhman, "Multi-Operated Associative Arithmetic"

K. Johnsen, "An IEEE Floating Point Arithmetic Implementation"

Session 7: Online and Pipeline Arithmetic

Y. Takefuji, T. Kurokawa and H. Aiso, "Fast Matrix Solver in GF(2)"
L. M. Ni and K. Hwang, "Vector Reduction Methods for Arithmetic Pipelines"

A. L. Grnarov and M. D. Ercegovac, "On-Line Multiplicative Normalization"

R. M. Owens and M. J. Irwin, "Numerical Limitations on the Design of Digital Online Networks"

Session 8: Special Topics

H. Kobayashi and R. D. Bonnell, "Arithmetic for a High-Speed Adaptive Learning Network Element"
A. Avizienis and C. S. Raghavendra, "Applications for Arithmetic Error Codes in Large, High-Performance Computers"
M. A. Bayoumi, G. A. Jullien and W. C. Miller, "Models for VLSI Implementation of Residue Number System Arithmetic Modules"

Session 9: Rational Arithmetic

R. B. Seidensticker, "Continued Fractions for High-Precision and High-Accuracy Computer Arithmetic"

K. Yoshida, "Floating-Point Recurring Rational Arithmetic System"

D. W. Matula and P. Kornerup, "An Order Preserving Finite Binary Encoding of the Rationals"
A. Miola, "A Unified View of Approximate Rational Arithmetic and Rational Interpolation"