8th IEEE Symposium on Computer Arithmetic

May 19-21, 1987
 Villa Olmo, Como, Italy

General Chair: Luigi Dadda
Program Co-Chairs: Mary Jane Irwin and Renato Stefanelli


[contents]

Preface

M. J. Irwin and R. Stefanelli, "The Eighth IEEE Symposium on Computer Arithmetic: Foreword"

Session 1: Opening Session - M. J. Irwin and R. Stefanelli, Chairman

Session 2: Signal and Image Processing - F. Rocca, Chairman

H. Umeo, "A Design of Time-Optimum and Register-Number-Minimum Systolic Convolver"

S. G. Smith and P. B. Denyer, "Synthesis of Area-Efficient VLSI Architectures for Vector and Matrix Multiplication"
R. S. Kao and F. J. Taylor, "Implementation of the Single Modulus Complex ALU"

I. D. Scherson and Y. Ma, "Vector Computations on Orthogonal Memory Access Multiprocessor System"

Session 3: VLSI Adder and Multipliers - H. Aiso, Chairman

T. M. Carter, "Structured Arithmetic Tiling of Integrated Circuits"

T. Han and D. Carlson, "Fast Area-Efficient VLSI Adders"
R. Sharma, "Area-Time Efficient Arithmetic Elements for VLSI Systems"
L. Ciminiera, "Parallel Multipliers Based on Horizontal Compressors"

Session 4: High-Speed Arithmetic Processors - B. Woo, Chairman

J. Fandrianto, "Algorithm for High Speed Shared Radix 4 Division and Radix 4 Square Root"

S. Kuninobu, T. Nishiyama, H. Edamatsu and T. Taniguchi, "Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation"

B. Bose, L. Pei, G. Taylor and D. Patterson, "Fast Multiply and Divide for a VLSI Floating-Point Unit"

V. Peng, S. Samudrala and M. Gavrielov, "On the Implementation of Shifters, Multipliers and Dividers in VLSI Floating Point Units"

Panel Session 5: Applications and Future Trends in Computer Arithmetic - K. Hwang, Moderator, H. Aiso, L. Dadda, T. Hull, M. J. Irwin, U Kulisch, D. Matula, G. Taylor and B. Woo, Panelists

Session 6: Elementary Function Evaluators - U. Kulisch, Chairman

M. Cosnard, A. Guyot, B. Hochet, J. M. Muller, H. Ouaouicha, P. Paul and E. Zysman, "The FELIN Arithmetic Coprocessor Chip"

J. R. Cavallaro and F. T. Luk, "CORDIC Arithmetic for an SVD Processor"
K. Hwang, H. C. Wang and Z. Xu, "Evaluating Elementary Functions with Chebyshev Polynomials on Pipeline Nets"

Session 7: Systolic Arithmetic Processors - J. Cody, Chairman

T. E. Hull and M. S. Cohen, "Toward an Ideal Computer Arithmetic"
F. W. J. Olver, "A Closed Computer Arithmetic"

F. W. J. Olver and P. R. Turner, "Implementation of Level-Index Arithmetic Using Partial Table Look-Up"

J. W. Demmel, "On Error Analysis in Arithmetic with Varying Relative Precision"

H. Hamada, "A New Real Number Representation and its Operation"

Session 8: Systolic Arithmetic Processors - R. Negrini, Chairman

B. Hochet and P. Quinton, "Systolic Solution of Linear Systems over GF(p) with Partial Pivoting"

P. T. Balsara and R. M. Owens, "Systolic and Semi-Systolic Digit Serial Multipliers"

B. Parhami, "Systolic Up/Down Counters with Zero and Sign Detection"

Session 9: On-Line Arithmetic Processors - G. Taylor, Chairman

P. K. G. Tu and M. D. Ercegovac, "A Radix-4 On-Line Division Algorithm"

H. Lin and H. J. Sips, "A Novel Floating-Point Online Division Algorithm"

M. D. Ercegovac and T. Lang, "On-Line Scheme for Computing Rotation Factors"

P. Kornerup and D. Matula, "A Bit-Serial Arithmetic Unit for Rational Arithmetic"

A. Colagrossi and A. Miola, "A Normalization Algorithm for Truncated P-ADIC Arithmetic"

Session 10: Fault-Tolerant Arithmetic Codes and Processors - D. Matula, Chairman

G. R. Redinbo, "Protecting Convolution-Type Arithmetic Array Calculations with Generalized Cyclic Codes"

J. E. Robertson, "Error-Detection and Correction for Addition and Subtraction through Use of Higher Radix Extensions of Hamming Codes"

V. Piuri, "Fault-Tolerant Systolic Arrays: An Approach Based upon Residue Arithmetic"

C. C. Wu, L. R. Tzeng and T. S. Wu, "Time-Redundant Fault-Masking in ALUs"

Session 11: Numerical Error Control - P. Kornerup, Chairman

G. Barrett, "A Formal Approach to Rounding"

J. Du Croz and M. Pont, "The Development of a Floating-Point Validation Package". (Not received in time for publication)

R. Kirchner and U. Kulisch, "Arithmetic for Vector Processors"

G. Schumacher, "Computer Arithmetic and Ill-Conditioned Algebraic Problems"