D. S. Phatak, I. Koren, "Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition", Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, April 14-16, 1999
J.-J. J. Lue, D. S. Phatak, "Area x Delay ( A·T ) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation", Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, April 14-16, 1999
D. S. Phatak, T. Goff, "Fast Modular Reduction for Large Wordlengths via One Linear and One Cyclic Convolution", Proceedings of the 17th IEEE Symposium on Computer Arithmetic, Cape Cod, Massachusetts, June 27-29, 2005