Prof. Vojin G. Oklobdzija
  ACSEL Director
  info [at] acsel-lab.com
 
 
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Energy Efficient Circuits
High Performance Adder
Low Power IC Design
Low Power Clocking Project
Clocked Storage Elements
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on Comp. Eng.
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Mission Statement
 
 

Advanced Computer Engineering Laboratory is engaged in solving problems related to high-performance and low-power computing systems with focus on VLSI chip engineering. We are experts in high-speed digital circuits as well as low-power design. We specialize in low-power digital circuit libraries and optimal relationship between computational energy and speed. Our broader expertise is also in Computer Architecture, Arithmetic, Media Signal Processing, Cryptography and System Architecture.

ACSEL is engaged in Technical Consulting and Expert Witness and Litigation Consulting.
Prof. Vojin G. Oklobdzija, ACSEL Director
ACSEL News
March 20, 2009: Christophe Giacomotto defended his PhD thesis titled: "Concurrent Design of Energy Efficient Clock Storage Elements and Clock Distribution Network"

May 21th, 2007:  IBM announced the fastest and most power efficient microprocessor, Power6, with clock frequency of 4.7GHz.

May 29th, 2007:  Xiao-Yan Yu defended her PhD dissertation: "Design of Power-Efficient Floating-Point Adder Blocks" used in IBM Power6.

June 2007: Our latest results on CSE selection in the system pipeline are available in IEEE Journal of Solid-State Circuits, Vol. 42, No. 6, "The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements"


Our recent research results in digital circuit optimization show power reduction of 30% is possible while maintaining the same speed.

 
ACSEL Research Projects Web Pages
 

Energy Efficient Circuits
We have developed optimization methods and design techniques which allow for 20-50% energy saving at iso-performance or 10-20% delay improvement at iso-energy for digital circuits. See: www.silicon-analytics.com

High Performance Adder
Using analysis done on existing high-performance adder designs, fast and energy-efficient adders using sub-100nm technology are being developed.

Low Power IC Design
Using optimization methodology, the best Energy-Delay designs of arithmetic units suitable for low power operation are developed.

Low Power Clocking Project
We demonstrated feasibility of dual-edge clocked storage elements for a synthesized core. The use of DECSE achieves 50% power reduction in clock distribution while maintaining the system throughput.

Clocked Storage Elements
We have the best Clocked Storage Elements in terms of speed and power in the industry. Please see our latest results on CSE selection in the system pipeline in this publication (pdf)

 
 
 
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