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[
Chandrakasan et. al. 92]
A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-Power CMOS Digital Design", IEEE Journal of Solid State Circuits, Vol. 27, No. 4, April 1992.
[Chandrakasan and Brodersen 95] A. Chandrakasan, R. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits", IEEE Proceedings, Vol. 83, No. 4, pp. 498-523, 1995.
[Dao et. al. 03] H. Q. Dao, B. R. Zeydel, V. G. Oklobdžija, "Energy Optimization of High-Performance Circuits", Proceedins of the 13th International Workshop on Power and Timing Modeling Optimization and Simulation, Torino, Italy, September 2003.
[Dao et. al. 03] H. Q. Dao, B. R. Zeydel, V. G. Oklobdžija, "Energy Minimization Method for Optimal Energy-Delay Extraction", Proceedins of the European Solid State Circuits Conference, ESSCIRC, Estoril, Portugal, September 2003.
[Farooqui et. al. 99] A. Farooqui, V. G. Oklobdžija, F. Chehrazi, "Multiplexer Based Adder for Media Signal Processing", International Symposium on  VLSI Technology, Systems and Applications, Taipei, Taiwan, June 1999.
[Harris et. al. 99] D. Harris, R. F. Sproull, I. E. Sutherland, "Logical Effort Designing Fast CMOS Circuits", Morgan Kaufmann Publishers, 1999.
[Horowitz et. al. 94] M. Horowitz, T. Indermaur, and R. Gonzales, "Low-Power Digital Design", Proceedings of the IEEE Simposium on Low-Power Electronics, 1994.
[Knowles 99] Simon Knowles, "A Family of Adders", Proceedings of the 14th IEEE Symposium on Computer Arithmetic, pp. 30-34, April 1999.
[Kogge and Stone 73] P. M. Kogge, H. S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurence Equations", IEEE Transactions on Computers, Vol. C-22, No. 8, pp. 786-793, 1973.
[Lee at. al. 94] W. Lee, U. Ko, P. T. Balsara, "A Comparative Study on CMOS Digital Curcuit Families for Low-Power Applications", Proceedings of the International Workshop on Low-Power Design, 1994.
[Nagendra et al. 94] C. Nagendra, R. M. Owens, M. J. Irwin, "Power-Delay Characteristics of CMOS Adders", IEEE Transactions on VLSI Systems, Vol. 2, No. 3, September 1994.
[Oklobdžija and Barnes 85] V. G. Oklobdžija, E. R. Barnes, "Some Optimal Schemes for ALU Implementation in VLSI Technology", Proceedings of the 7th IEEE Symposium on Computer Arithmetic, pp. 2-8, 1985.
[Oklobdžija et. al. 03] V. G. Oklobdžija, B. R. Zeydel, H. Dao, S. Mathew, R. Krishnamurthy, "Energy-Delay Technique for High-Performance Microprocessor VLSI Adders", Proceedings of the 16th IEEE Symposium on Computer Arithmetic, Santiago de Compostela, Spain, June 2003.
[Sproull and Sutherland 91] R. F. Sproull, I. E. Sutherland, "Logical Effort: Designing for Speed on the Back of an Envelop", IEEE Advanced Research in VLSI, C. Sequin (editor), MIT Press, 1991.
[Stojanovic et. al. 02] V. Stojanović, D. Marković, B. Nikolić, M. A. Horowitz, R. W. Brodersen, "Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Opmization", Proceedins of the 28th European Solid State Circuits Conference, ESSCIRC, Florence, Italy, September 2002.
[Tan and Allen 94] C. H. Tan, J. Allen, "Minimization of Power in VLSI Circuits using Transistor Sizing, Input Ordering and Statistical Power Estimation", In Proceedings of the International Workshop on Low Power Design, pp. 75-80, April 1994.
[Veendrick 84] H. J. M. Veendrick, "Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits", IEEE Journal of Solid State Circuits, Vol. SC-19, pp. 468-473, August 1984.
[Zyuban and Strenski 02] V. Zyuban, P. Strenski, "Unified Methodology for Resolving Power-Performance Tradeoffs at the Microarchitectural and Circuit Levels", IEEE Symposium on Low Power Electronics and Design, 2002.
[Zyuban et. al. 04] V. Zyuban, D. Brooks, V. Srinivasan, M. Gschwind, P. Bose, P. N. Strenski, P. G. Emma, "Integrated Analysis of Power and Performance for Pipelined Microprocessors", IEEE Transactions on Computers, Vol. 53, Issue 8, August 2004.



 

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