As technology continues to
scale, power consumption is becoming limiting factor over the performance in
digital CMOS designs. Portability of handhelded products demands for
ultra-low power operation regime, both in active and standby mode.
Technological approach to lowering the power consumption has led to the
usage of SOI devices which allow for power reduction due to their inherent
advantages over the bulk devices: low voltage operation, dynamic threshold
voltage modulation, sharp subthreshold slope, reduced parasitic
capacitances, lower temperature sensitivity, etc.
Main objective of this research
is to develop optimization methodology for power efficient processor
components. Architectural and circuit levels with different design styles
are exploited and optimization is performed, obtaining the best energy-delay
designs. While still meeting the performance requirements, 2-fold power
reduction can be achieved.
Current state-of-the-art
innovations in energy-delay efficient design techniques could be also found
in the related projects of Acsel laboratory.
