Storage elements commonly used for the synchronization and data storage in pipelines and other applications are transparent latches and flip-flops.
Latch is a level-sensitive element with following functional behavior: when control signal (clock) is at the active level, the latch is transparent, i.e. the output follows any transition at the input, Figure 1. When the clock is at the inactive level, the latch is opaque, i.e. it holds the output state. The transition of the clock signal from the active level to the inactive level is referred to as latching edge, since the state of the output cannot be changed after this edge. Similarly, we define the releasing edge of the clock as the transition of the clock signal from the inactive level to the active level. Depending on the values of the active and inactive level of the control signal, a latch can be high-level transparent (when active level is logical high) or low-level transparent (when active level is logical low).
The common configurations that use transparent latches are pulsed latches and master-slave latches. Pulsed latch (PL) is a latch configuration in which a short pulse, produced after one edge of the clock, is used as a clock input to the latch, Figure 2. In this arrangement, the latch is transparent only during a short time after the active clock edge, while it is opaque otherwise, regardless of the timing waveform of the clock. In other words, the latch behaves as an edge-triggered storage element (see flip-flop below).
Figure 1. High-level transparent latch and timing diagrams
Master-slave latch (MS latch) is a particular arrangement of transparent latches in which two latches are connected in series and clocked with two independent clocks phases, Figure 3. The input data D is captured at the latching edge of the master clock and released to output Q at the releasing edge of the slave clock. The timing parameters and the behavior of the master-slave latch depend on the timing between master and slave clock phases, as it will be shown later.
Most common implementation of master-slave latch consists of two serially connected identical latches transparent on opposite levels of the input clock (complementary clock phases). In this way, a master-slave latch behaves as an edge-triggered storage element (see flip-flop below). If the master latch is transparent on the high level of the clock, and the slave latch is transparent on the low level of the clock, resulting MS latch is “falling-edge triggered”, otherwise it is “rising-edge triggered”.
Flip-flop is an edge-sensitive element with following behavior: the output captures the value of the input either after the low-to-high transition of the clock, or after the high-to-low transition of the clock; otherwise, the flip-flop is non-transparent, i.e. it holds the captured value at the output. The transition of the clock that causes the change of the output is referred to as capturing edge of the clock. Depending on which clock edge is capturing, a flip-flop can be rising-edge triggered, Figure 5, or falling-edge triggered.
Structurally, a flip-flop consists of two functional stages (Figure 4b, [Oklobdzija2003]):
· Pulse generator, producing a pulse synchronous to the active clock edge, depending on the input value to be captured.
As opposed to the operation of a pulsed latch, the pulse created by the pulse generator of a flip-flop contains all information about new data to be captured, and the second-stage latch is used only to create a static output. Such pulse need not have determined short width, and it can be chosen to facilitate the design of both pulse generator and the latch.
Dual-edge triggered storage element is an edge-sensitive element that captures the value of the input after both low-to-high and high-to-low clock transitions. Otherwise, the storage element is non-transparent, i.e. it holds the captured value at the output.
A dual-edge triggered storage element can be classified as [Nedovic2002a, Oklobdzija2003]:
A latch is characterized by the following parameters:
Following are the basic timing parameters of a flip-flop:
Dual-edge triggered storage elements apply all parameters defined for the single-edge triggered storage elements to the both clock edges. It is a custom practice that the worse of the parameters for the two edges is used as the only timing parameter. As the timing parameters for both clock edges should always be taken into account.