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- V. G. Oklobdzija, V. Stojanovic, D. Markovic, N. Nedovic,
"Digital
System Clocking:
High-Performance and Low-Power Aspects",
John Wiley, January 2003.
- B. Nikolic, V. G. Oklobdzija, "
A Single-Phase Clock High-Performance BiCMOS Latch", Proceedings of the
7th International Symposium on IC Technology, Systems &
Applications, September 10-12, 1997, Singapore.
- B. Nikolic, V. G. Oklobdzija, "
Low Voltage BiCMOS TSPC Latch for High Performance Digital System",
1998 IEEE International Symposium on Circuits and Systems, May 31 - June 3
1998, Monterey, California.
- V. Stojanovic, V. G. Oklobdzija, R. Bajwa,
"A Unified Approach in the Analysis of Latches and Flip-Flops for Low-Power",
International Symposium on Low Power Electronics and Design, August 10-12,
1998, Monterey, California.
- V. Stojanovic, V. G. Oklobdzija, R. Bajwa,
"Comparative analysis of Master-Slave Latches and Flip-Flops for HIgh-Performance
VLSI Systems", International Conference on Computer Design, October 5-7,
1998, Austin, Texas.
- B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J.
Chiu, M. Leung,
"Sense Amplifier Based Flip-flop," 1999 IEEE International Solid-State
Circuits Conference, San Francisco, February 1999.
- V.Stojanovic and V.G. Oklobdzija,
"Comaparative Analysis of Master-Slave Latches and Flip-Flops for
High-Performance and Low-Power VLSI Systems," IEEE Journal of Solid-State
Circuits, Vol.34, No.4, April 1999.
- B. Nikolic, V. G. Oklobdzija,
"Design and Optimization of Sense Amplifier-Based Flip-Flops", 25th
European Solid-State Circuits Conference, Duisburg, GERMANY, 21-23 September
1999.
- B. Nikolic, V. G. Oklobdzija,
V. Stojanovic, W. Jia, J. Chiu, M. Leung,
"
Improved Sense Amplifier-Based Flip-Flop: Design and Measurements",
IEEE Journal of Solid-State Circuits,
Vol. 35, No. 6, June
2000.
- N. Nedovic, V. G. Oklobdzija,
“Hybrid Latch Flip-Flop with Improved Power Efficiency”, Proceedings
of the Symposium on Integrated Circuits and Systems Design, SBCCI2000, Manaus,
Brazil, September 18-22, 2000.
- N. Nedovic, V. G. Oklobdzija,
“Dynamic
Flip-Flop with Improved Power”, Proceedings of the 26th
European Solid-State Circuits Conference, ESSCIRC’2000, Stockholm, Sweden,
September 19-21, 2000.
- N. Nedovic, V. G. Oklobdzija,
“Dynamic
Flip-Flop with Improved Power”, Proceedings of the International
Conference on Computer Design, ICCD 2000, Austin, Texas, September 18-20,
2000.
- Nikola Nedovic, Marko Aleksic and Vojin G. Oklobdzija, “Conditional
Techniques for Small Power Consumption Flip-Flops”, Proceedings of the
8th IEEE International Conference on Electronics, Circuits and
Systems, Malta, September 2-5, 2001.
-
Nikola Nedovic, Marko Aleksic and
Vojin G. Oklobdzija,
“Timing Characterization of Dual-Edge Triggered Flip-Flops”,
Proceedings of the International Conference on Computer Design, ICCD 2001,
Austin, Texas, September 23-26, 2001.
-
Nikola Nedovic,
Marko Aleksic, Vojin G. Oklobdzija, “Comparative
Analysis of Double-Edge versus Single-Edge Triggered Clocked Storage Elements”,
2002 IEEE International Symposium on Circuits and Systems, Scottsdale,
Arizona, May 26-29, 2002.
- Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija,
“Conditional Pre-Charge Techniques for Power-Efficient Dual-Edge Clocking”,
Proceedings of the International Symposium on Low-Power Electronics and
Design, Monterey, California, August 12-14, 2002.
-
Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija, Marko
Aleksic,
“A Low Power Symmetrically Pulsed Dual Edge-Triggered Flip-Flop”,
Proceedings of the 28th European Solid-State Circuits Conference,
Florence, ITALY, September 24-26, 2002.
-
N.
Nedovic, V. G. Oklobdzija, W. W. Walker, “A Clock Skew Absorbing Flip-Flop”,
2003 IEEE International Solid-State Circuits Conference Digest of Technical
papers, San Francisco, February 2003.
-
N.
Nedovic, "Clocked Storage Elements for High-Performance Applications", Ph.D.
Dissertation, 2003.
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