In order to synchronize the operation and perform the tasks in orderly manner, complex sequential digital designs use global periodical signals with known timing. Common name for these signals is clock signals, and the part of a digital circuit that performs this synchronization using clock signals is called clocking subsystem. The timing of the clock signal provides a reference at which the state of the digital system is changed. This timing reference is essential for the operation of the sequential circuits. By using clock signals, clocking subsystem allows coherent functioning of the entire design, prevents overwriting the data before it is consumed, and ensures its delivery at a known time.

Clocking subsystem consists of clock generation system, clock distribution system, and clocked storage elements, or storage elements. Clock generation and clock distribution systems supply the clock signal to the points where it is consumed by the storage elements. The timing and number of clock signals, storage elements, and the way they are connected determine how the synchronization is performed, and thus establish the clocking strategy. Common clocking strategies used in microprocessors are based on single phase clocking or multiple phase clocking [Unger1986]. Single-phase clocking is the strategy where only one clock signal is distributed over the design and used by all storage (synchronization) elements. Multiple-phase schemes use known timing relationships between clock phases to relax the timing requirements and increase the performance of the data path.

In early years of the digital electronic industry, importance of the clocking subsystem was modest, as it occupied only a small portion of the timing and power of the system. Clock frequencies were in a range of megahertz, clock was distributed over several printed boards, and longest paths in logic consisted of hundreds of logic gates. With faster operation, widespread use of pipelined designs, RISC and superscalar machines and clocked dynamic logic, significance of the clocking subsystem increased significantly. The trend of frequency scaling beyond the speed-up provided by the technology dictates a decrease of number of logic gate delays per clock cycle and a continuous increase of timing overhead for clocking relative to the clock period. Recently, as the operating frequency of the high-speed applications exceeds 1GHz and the power consumption is in range of 100W ([Jain2001, Hofstee2000]), design of clocking subsystem becomes crucial for correct operation and performance of the entire design.

With the increase of performance, speed and complexity of VLSI circuits, clocking strategies become progressively diverse and innovative in order to provide required performance. Design of each component of the clocking subsystem grows in complexity and develops almost as an independent research field. 


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