Clock Distribution



Generated high-frequency clock signal must be distributed so that it is supplied to the terminal points (storage elements) ideally at the same time. In addition, since the clock typically must be brought to very large number of storage elements, the clock distribution must greatly amplify clock signal before it is delivered to the terminal points. Typically, the clock is distributed using matched paths consisting of a number of drivers in a tree configuration. The signals produced by the group of drivers at the same distance from the clock generator (same level of clock distribution tree) ideally have identical timing. Some examples of common clock distribution schemes, shown in Figure 1, are binary tree, H‑tree, and X-tree [Oklobdzija1999, Chandrakasan2001].

Figure 1. Examples of clock distribution network: a) binary tree, b) H-tree, c) X-tree

The drivers in the clock tree frequently perform other functions in addition to the signal amplification, such as scan and clock gating. The clock trees may contain adjustment elements that allow fine tuning of the clock arrival, either to equalize the delays of individual paths of the clock, such as active de-skewing circuits [Rusu2000, Kurd2001], or to intentionally allow additional time slack for the critical parts in the logic [Fishburn1990, Friedman1995]. An effective method for equalizing the clock arrival time at the storage elements is use of the clock grid [Bailey1998, Heald2000]. The clock grid connects the outputs of a number of clock distribution drivers of the same level, thus averaging their delays. Dense wire grid imposes a large capacitive load to the clock distribution tree and causes large power consumption. For this reason, clock grid is today used mainly in high-performance processors, where tighter timing specification of the clock and extra performance justify the additional power consumption.


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