Rapidly increasing clock frequencies contribute directly to clock-related power consumption of microprocessors. The power consumed by the clock can reach half of the processor power, which is growing at roughly 20% per year. Furthermore, with the growing popularity of mobile computing devices, and the advent of ubiquitous wireless networking, there has been a premium placed on low power design methodologies. Reducing the power consumption of a design translates directly into increased battery life of the mobile device. This has led to the design of VLSI systems of increasing complexity and increasingly restrictive power budgets.
There have been many successful approaches to reducing power consumption of Systems on a Chip (SoCs). Several of these approaches directly tackle the major culprit of power consumption in digital system designs; namely the clock distribution network. Clock gating has become widely used as a method of intermittently shutting down portions of an SoC or microprocessor when those functional blocks are not required to be in use. For any design there is a limit to how much clock gating is feasible and once this limit is reached designers must look elsewhere for techniques to further lower power consumption. Another method in use for reducing the power consumption of a design is Dynamic Voltage Scaling (DVS). This method is similar to clock gating in the sense that the system intermittently deminishes its performance capability when peak performance is not required. DVS accomplishes this by reducing the operating voltage of the entire design. This method has been successful, but its future is limited by scalability issues. As process geometries shrink and supply voltages are reduced, there is less and less power supply margin for doing DVS.
Another approach to reduce clock-related power is to use dual-edge triggered storage elements (DET-CSE) in place of single edge-triggered storage elements (SET-CSE), similar to the use of DDRAM to increase memory bandwidth. Dual-edge clocking can achieve the same throughput at half the clock frequency and half the clock-related power consumption as compared to the use of single-edge clocked storage elements. Unlike DVS, this technique is very ammenable to technology scaling, and could be used in conjunction with the benefits of clock gating.
Simple analysis shows that halved clock frequency would reduce clock-related power to about half of the original design, and significantly reduce total power consumption in the VLSI design. Less aggressive clock subsystems can be built, further reducing power consumption and allowing for the design towards minimizing the clock uncertainties. However, in order to cash in on the power savings achieved in the clock distribution tree, these newly introduced storage elements should be comparable to their single-edged counterparts in power consumption and the load on the clock distribution tree.
Typically, a circuit required to capture data at both clock edges is more complex and/or slower compared to a SET-CSE. A challenge of DET-CSE design is to minimize this delay degradation in order to exploit the full potential of clocking at half the frequency. Also, in order to keep timing overhead low, dual-edge clocking requires tight control of the clock duty cycle and uncertainties of both clock edges. Thus, the ability to absorb clock uncertainties is essential.