bulletMarch 12 Presentation

Online References

bulletLeon SPARC core home page:
bulletLeon SPARC user group:
bulletSynopsys User Group (ESNUG):

Software Files

bulletSynthesis Scripts
bulletEnvironment setup for synopsys
bulletDC setup script for 0.18um CMOS library
bulletDC synthesis Script 
bulletDC Power analysis Script
bulletNetlists (hierarchical verilog)
bulletSingle-edge triggered design
bulletDual-edge triggered design
bulletSynthesis Generated Report files
bulletSingle-edge triggered timing report
bulletDual-edge triggered timing report
bulletAutomated Characterization & Model Generation Script
bulletRelease 2.1
bulletModel Files
bulletSynopsys (.lib)

Related Work

  1. Vojin G. Oklobdzija, "Clocking and Clocked Storage Elements in Multi-GHz Environment", Invited paper, 12th International Workshop on Power And Timing Modeling, Optimization and Simulation, Sevilla, SPAIN, September 11-13, 2002. Proceedings (Lecture Notes in Computer Science Vol.2451). Springer-Verlag. 2002, pp.128-45. Berlin, Germany.

  2. Oklobdzija VG, Sparso J. "Future directions in clocking multi-GHz systems". ISLPED'02: Proceedings of the 2002 International Symposium on Lower Power Electronics and Design (IEEE Cat. No.02TH8643). ACM. 2002, pp.219. New York, NY, USA.

  3. Nikola Nedovic, Marko Aleksic and Vojin G. Oklobdzija, "Timing Characterization of Dual-Edge Triggered Flip-Flops", Proceedings of the International Conference on Computer Design, ICCD 2001, Austin, Texas, September 23-26, 2001.

  4. Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan, and James D. Meindl, "Optimal Synchronization Energy Allocation for CMOS Integrated Systems", 3rd International Symposium on Quality Electronic Design, March 18-20, 2002, San Jose, California, USA.

  5. Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija, "Comparative Analysis of Double-Edge versus Single-Edge Triggered Clocked Storage Elements", 2002 IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, May 26-29, 2002.

  6. Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija, Marko Aleksic, "A Low Power Symmetrically Pulsed Dual Edge-Triggered Flip-Flop", Proceedings of the 28th European Solid-State Circuits Conference, Florence, ITALY, September 24-26, 2002.

  7. N. Nedovic, V. G. Oklobdzija, W. W. Walker, "A Clock Skew Absorbing Flip-Flop", 2003 IEEE International Solid-State Circuits Conference Digest of Technical papers, San Francisco, February 2003.

  8. Zyuban V. "Optimization of scannable latches for low energy". [Journal Paper] IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, vol.11, no.5, Oct. 2003, pp.778-88. Publisher: IEEE, USA.









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Last updated: 07/28/04.