SET Power Analysis
DET power analysis


To date, we have synthesized both the SET LEON design and the DET LEON design using one size of flip-flops.  Initial power calculations show that we are achieving roughly half of the clock power as expected. 

For the SET LEON design, Transmission Gate Master Slave (TGMS) latches are used for the SETFF.  For the DET LEON design, the Symmetric Pulse Generator Flip-Flops (SPGFF) are used for the DETFF.  Results of characterization show how these two devices perform over various loads and input conditions. 

In the links to the left, you will find the characterization of the TGMS and the SPGFF, the power analysis of the SET LEON processor, and the power analysis of the DET LEON processor

Aggressive timing synthesis of the two cores results in the SPGFF achieving an operating frequency of 309MHz and the TGMS a frequency of 282MHz. This shows a 10% improvement in performance for the SPGFF versus the TGMS designs. The timing reports generated from synthesis can be found in the archive. Both designs fail timing when the operating frequency is increased by 1MHz. The 10% improvement in the design performance matches the delay improvement that the SPGFF cell is shown to have over the TGMS cell from the characterization.

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Last updated: 07/28/04.