We would like to show the power savings in each component of the
clock sub-system and demonstrate the feasibility of the DET-CSE
concept. The problems we are addressing are applicable to
high-performance processors, read-channel and DSP communication systems
characterized with very high-speed clock and shallow pipeline in an
environment where computation can be distributed among several parallel
units. We feel these issues have not been addressed sufficiently in the
current research in VLSI.
Another important consideration in the investigation of new clocking strategies is the impact that the proposed enhancement would have on existing design methodologies. If a new strategy requires a new set of design tools, or design steps that add significantly to the design time, then the benefits of such strategies must be carefully weighed with the cost and risk of altering the design flow. Our goal is to skirt this issue entirely, by demonstrating that DET-FFs can be incorporated into designs with the same tools and same design methodologies used in existing automated design flows.
Our objective is to show that DET-CSEs offer distinct advantages over SET-CSE and can be integrated into existing design flows with minimal changes. We will take an openly available, synthesizable, microprocessor design (the LEON2 SPARC V8 compatible processor), synthesize the core using SET-CSEs and traditional techniques, integrate our DET-CSEs into the design in place of SETSEs, perform a power comparison of the two designs and demonstrate the viability of the DET-CSE design.
There are three main portions to this project: