Project Abstract
ACSELab is currently investigating the integration of dual-edge
triggered clock storage elements
(DET-CSE)
into
standard cell, synchronous, sythesizable designs, which traditionally
utilize single-edge triggered clock storage elements
(SET-CSE). This investigation builds on previous and on-going
research at
ACSEL demonstrating DET-CSEs that are more tolerant to clock skew and
jitter and capable of incorporating logic and scan yet maintaining
similar speed, power consumption and loading characteristics as
SET-CSEs (see related work).
Our objective is to show that DET-CSEs offer distinct advantages over
SET-CSE and
can be integrated into existing design flows with minimal changes. We
will take
an openly available, synthesizable, microprocessor design (the LEON2
SPARC
V8 compatible processor, see links for detailed information),
synthesize the core using SET-CSEs and traditional techniques,
integrate our DET-CSEs into the design in place of SETSEs, perform a
power
comparison of the two designs and demonstrate the viability of the
DET-CSE
design. The project roadmap has a detailed overview of the
methodologies and tool flows used to acheive these goals.
