
The total power savings of the
implementation with DETCSEs is a function of the power characteristics
of the particular DETCSE as it compares to the SETCSE. The
following parameters of the DETCSE must be compared to the SETCSE:
In a synthesized design, the delay and drive characteristics of the combinatorial and sequential elements in standard cell library determine the netlist generated by the synthesis tool, and the synthesis tool's ability to meet timing constraints. Thus, not only does the loading of the DETCSE directly impact the overall power of the design, but also the delay and drive characteristics of the particular DETCSE indirectly impact the power by altering the generated netlist due to timing and optimization decisions made by the synthesis tool. Analysis of the DETCSE synthesis generated netlist is shown below in table 1. The power calculation for the clock tree uses the same methods employed for the SETCSE design with Htree estimate. The power is calculated using half the clocking frequency of the SETCSE design. Table 1  Power consumption of
Architectural Blocks in LEON2 processor with DETCSEs
Figure 1 shows the proportion of power consumed by the clock tree, processor core, and memory
Figure 2  Comparison of DET and SET core and clock tree power.

