DET power analysis


The total power savings of the implementation with DET-CSEs is a function of the power characteristics of the particular DET-CSE as it compares to the SET-CSE.  The following parameters of the DET-CSE must be compared to the SET-CSE:
  1. clock pin loading (clock pin switching power) - modeled as the alpha coefficient (see power analysis methodology and tool flow)
  2. Internal power consumption of CSE.
  3. Data pin loading (data pin switching power)

In a synthesized design, the delay and drive characteristics of the combinatorial and sequential elements in standard cell library determine the netlist generated by the synthesis tool, and the synthesis tool's ability to meet timing constraints.  Thus, not only does the loading of the DET-CSE directly impact the overall power of the design, but also the delay and drive characteristics of the particular DET-CSE indirectly impact the power by altering the generated netlist due to timing and optimization decisions made by the synthesis tool.  

Analysis of the DET-CSE synthesis generated netlist is shown below in table 1.  The power calculation for the clock tree uses the same methods employed for the SET-CSE design with H-tree estimate.  The power is calculated using half the clocking frequency of the SET-CSE design. 

Table 1 - Power consumption of Architectural Blocks in LEON2 processor with DET-CSEs
Architectural Block
Power (mW)
Microprocessor Core (IU, Timers, UARTs, Memory controller, AMBA bus arbitration, Interrupt Controller)
Memory Blocks: Register File (136x32-bit Dual-ported SRAM), Instruction Cache - 16-kByte single-port SRAM (plus 512x26-bit SRAM Tags), Data Cache - 16-kByte single-port SRAM (plus 512x26-bit SRAM Tags)
Clock Tree (loading of CSEs, wire-loading estimate, and estimate of internal power consumed by clock buffer tree at half SET-CSE clocking frequency)
Total Power

Figure 1 shows the proportion of power consumed by the clock tree, processor core, and memory

Figure 1 - DET-CSE netlist power proportions

  Figure 2 shows the power consumption of just the core and the clock tree for both the DET and SET processors. 

Figure 2 - Comparison of DET and SET core and clock tree power.


Home | Background | Project Details | Members | Schedule | Archive | Results

Last updated: 07/28/04.