SET Power Analysis


The power breakdown of various components in the design of the LEON2 Processor is shown in table 1.  The power data is calculated using Power Compiler and 0.5clk rate toggle rate applied to all the primary inputs of the design.  The tool propagates the toggle rate applied to the primary inputs throughout the netlist hierarchy.  The power excludes the power consumed by the I/O pads.  Table 1 shows the power consumed by each architectural block.

Table 1 - Power consumption of Architectural Blocks in LEON2 processor
Architectural Block
Power (mW)
Microprocessor Core (IU, Timers, UARTs, Memory controller, AMBA bus arbitration, Interrupt Controller)
Memory Blocks: Register File (136x32-bit Dual-ported SRAM), Instruction Cache - 16-kByte single-port SRAM (plus 512x26-bit SRAM Tags), Data Cache - 16-kByte single-port SRAM (plus 512x26-bit SRAM Tags)
Clock Tree (loading of CSEs, wire-loading estimate, and estimate of internal power consumed by clock buffer tree)
Total Power

Figure 1 shows the proportion of power consumed by each architectural block.  Figure 1 includes the cache memories (total cache is both data and instruction) which assume half reads/half writes every cycle to the instruction cache, and half reads/half writes to the data cache every second cycle (based on instruction mix of 50% load/store operations).  

Figure 1 - Power breakdown of LEON2 Processor

As shown in Figure 1, the caches are large consumers of power.  The register file is also a large consumer of power. This is due in part to the SPARC architecture and support of register windows and also in part to the implementation. In this design there are 136 32-bit registers, more than most RISC processors. In this implementation, the 136 32-bit register memory array is instantiated twice from the standard cell RAM generators to acheive the functionality of two simultaneous read ports. Thus, the implementation of the register file is in effect very large and consumes a large portion of the power.    Figure 2 shows just the core and clock tree power of the LEON2 Processor

Figure 2 - Power breakdown of LEON2 Processor excluding data and instruction caches

Clock Distribution Network calculation details

The method for estimating the power consumed in the clock distribution method is detail in the power analysis methodology section of the project roadmap.  Some of the equations are reproduced below for convenience.  The estimate is based on the estimated loading of an H-tree distribution network.  The values of the parameters used are detailed below.

The first step is to calculate an estimate of the Capacitance of the clock distribution network, or the H-tree.  This is shown below.

The next step is to include the capacitance estimate in the total power equation and calculate the estimated power consumed in the H-tree.

The power of the clock buffers is estimated below.  Since the final topology of the clock distribution network is not known, there is no need to use the precise numbers as shown in the equation above.  Thus an approximate number of buffers is used.  The calculation of the power of the clock buffer tree is shown below.

The total estimated power of the clock distribution network is calculated below.



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Last updated: 07/28/04.