Project Timeline

07/02/04

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Spring 2004

bulletPreliminary Evaluation of state-of-the designs in 130nm CMOS technology.

Summer 2004

bulletPerform studies on trade-offs of adders implemented using different logic families in sub-100nm process technology.
bulletProvide optimization methodology of adder structure in that technology
bulletImplement the resultant optimal adder
bulletPrepare test chip

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