Preliminary Results

07/02/04

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This page shows preliminary results. It is still heavily under construction.

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Adder Setup:
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Process Technology: 130nm CMOS Technology

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Analysis is done using the method of Logical Effort

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Equivalent of 1mm wire load is added to the outputs

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Curves are estimated by varying input driver size

 

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Copyright Advanced Computer Systems Engineering Laboratory, 2004

This site was last updated 07/01/04