Adder Designs
Preliminary Results
Related Projects
Project Timeline


Paper References:

  1. A. Weinberger and J. L. Smith, “A Logic for High-Speed Addition”, National Bureau of Standards, Circ. 591, pp. 3-12, 1958.

  2. Kilburn T., D. B. G. Edwards, and D. Aspinall, “Parallel Addition in Digital Computers: A New Fast “Carry” Circuit”, Proceedings of IEE, Volume 106, pt B, p.464, September 1959.

  3. J. Sklansky, “Conditional-Sum Addition Logic”, IRE Transactions on Electronic Computers, EC-9, p 226-231, 1960.

  4. O. J. Bedrij, “Carry-Select Adder”, IRE Transactions on Electronic Computers, p. 340-344, 1962.

  5.  P.M. Kogge and H.S. Stone, “A parallel algorithm for the efficient solution of a general class of recurrence equations”, IEEE Trans. Computers, Vol. C-22, No. 8, 1973, pp.786-793.

  6. H. Ling, “High-Speed Binary Adder”, IBM J. Res. Dev., vol.25, p.156-66, 1981.

  7. R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”, IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982.

  8. V. G. Oklobdzija and E. R. Barnes, “Some Optimal Schemes For ALU Implementation in VLSI Technology”, Proceedings of the 7th Symposium on Computer Arithmetic ARITH-7, pp. 2-8, Reprinted in “Computer Arithmetic”, E. E. Swartzlander, (editor), Vol. II, pp. 137-142, 1985.

  9. T. D. Han and D. A. Carlson, “Fast Area-Efficient VLSI Adders,” 8th symposium on Computer Arithmetic, May 1987.

  10. R. W. Doran, “Variants of an Improved Carry Look-Ahead Adder”, IEEE Transactions on Computers, Vol. 37, No. 9, September 1988, pp. 1110-1113.

  11. V. G. Oklobdzija and E. R. Barnes, “On Implementing Additions in VLSI Technology”, IEEE Journal of Parallel and Distributed Computing, No. 5, pp. 716-728, 1988.

  12. B. D. Lee and V. G. Oklobdzija, “Improved CLA Scheme with Optimized Delay”, Journal of VLSI Signal Processing, Vol. 3, No. 4, pp 265-274, 1991.

  13. A. Naini, D. Bearden and W. Anderson, “A 4.5ns 96b CMOS Adder Design”, Proceedings of the IEEE Custom Integrated Circuits Conference, p. 25.5.1-25.5.4, May 3-6, 1992.

  14. S. Naffziger, “A Sub-Nanosecond 0.5mm 64b Adder Design”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco, 8-10 Feb. 1996, p. 362-363.

  15. A. Farooqui, V. G. Oklobdzija and F. Chehrazi, “Multiplexer Based Adder for Media Signal Processing”, 1999 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, June 8-10, 1999.

  16. J. Park, et. al, “470ps 64bit Parallel Binary Adder”, Proceedings of 2000 Symposium on VLSI Circuits, 2000.

  17. S. Knowles, “A Family of Adders”, Proceedings of 15th IEEE Symposium on Computer Arithmetic, June 11-13, 2001.

  18. S. K. Mathew, R.K. Krishnamurthy, M.A. Anders, R. Rios, K.R. Mistry, and K. Soumyanath, “Sub-500-ps 64-b ALUs in 0.18-mm SOI/bulk CMOS: design and scaling trends”, IEEE Journal of Solid-State Circuits, Volume 11, Nov. 2001.

  19. S. Mathew, M. Anders, R. K. Krishnamurthy and S. Borkar, “A 4-GHZ 130-nm address generation unit with 32-bit sparse-tree adder core”, IEEE Journal of Solid-State Circuits, Volume 38, Issue 5, May, 2003.

  20. S. Mathew, M. Anders, B. Bloechel, T. Nguyen, R. Krishnamurthy and S. Borkar, “A 4GHZ 300mW 64b Integer Execution ALU with Dual Supply Voltage in 90nm CMOS”, Digest of Technical Papers of 2004 IEEE International Solid-State Circuit Conference, San Francisco, February, 2004.

  21. V. G. Oklobdzija, B. R. Zeydel, H. Dao, S. Mathew, R. Krishnamurthy, “Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders”, Proceedings of the International Symposium on Computer Arithmetic, ARITH-16, Santiago de Compostela, SPAIN, June  15-18, 2003.

  22. Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija, “Energy Minimization Method for Optimal Energy-Delay Extraction”, Proceedings of the European Solid-State Circuits Conference,  ESSCIRC 2003, Estoril, PORTUGAL, September 16-18, 2003.

  23. Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija, “Energy Optimization of High-Performance Circuits”, Proceedings of the 13th International Workshop on Power And Timing Modeling, Optimization and Simulation, Torino, Italy, September 10-12, 2003.

Patent References:

  1. T. W. Houston, P. W. Bosshart and C. H. Shaw, “Compound Domino CMOS Circuit”, U.S. Patent No. 5,015,882, Issued: May 14, 1991.  

  2. S. Naffziger, "High Speed Addition Using Ling's Equations and Dynamic CMOS Logic", U.S. Patent No. 5,719,803, Issued: February 17, 1998.

  3. H. Ngo, S. H. Dhong and J. A. Silberman, "High-Speed Binary Adder", U.S. Patent No. 5,964,827, Issued: October 12, 1999.

Book References:

  1. K. Hwang, “Computer Arithmetic: Principles, Architecture and Design”, John Wiley & Sons, 1979.

  2. V. G. Oklobdzija, “High-Speed VLSI Arithmetic Units: Adders and Multipliers”, in “Design of High-Performance Microprocessor Circuits”, Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000.

  3. M. J. Flynn and S. F. Oberman, "Advanced Computer Arithmetic Design", John Wiley & Sons, 2001.

Home | Introduction | Adder Designs | Preliminary Results | Members | References | Related Projects | Project Timeline

Copyright Advanced Computer Systems Engineering Laboratory, 2004

This site was last updated 07/01/04