March 20, 2009: Christophe Giacomotto defended his PhD thesis titled:
"Concurrent Design of Energy Efficient Clock Storage Elements and Clock
May 21th, 2007: IBM announced the fastest and most power efficient
with clock frequency of 4.7GHz.
May 29th, 2007: Xiao-Yan Yu
defended her PhD dissertation: "Design of Power-Efficient Floating-Point
Adder Blocks" used in
June 2007: Our latest results on CSE selection in the system pipeline are available in IEEE Journal of Solid-State Circuits, Vol. 42, No. 6, "The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements"
Our recent research results in digital circuit optimization show power reduction of 40% is possible while maintaining the same speed.
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