
Publications
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1970 to 1979
 V. G. Oklobdzija and N. Konjevic, "Spectroscopy Of Axisymmetric Plasma Sources", Proceedings of the Eleventh International Conference on Phenomena in Ionized Gases, p. 449, 1973.
 V. G. Oklobdzija and N. Konjevic, "RefractiveRay Bending In AxiallySymmetric Plasma Sources", Proceedings of the International Conference on the Physics of Ionized Gases, 1974.
 V. G. Oklobdzija and N. Konjevic, "RefractiveRay Bending In AxiallySymmetric Plasma Sources", Journal of Quantitative Spectroscopy and Radiative Transfer, Vol. 14, pp. 389394, 1974.
1980 to 1989
 V. G. Oklobdzija, "Up/Down Display Counter Counts Over Pos/Neg Range", Digital Design, pp. 9495, 1981.
 V. G. Oklobdzija and M. D. Ercegovac, "Testability Enhancement Of VLSI Using Circuit Structures", Proceedings of IEEE International Conference on Circuits and Computers, ICCC '82, pp. 198201, 1982.
 V. G. Oklobdzija and M. D. Ercegovac, "An OnLine Square Root Algorithm", IEEE Transactions on Computers, Vol. C31, No. 1, pp. 7075, 1982.
 V. G. Oklobdzija, "Design Note. OptoIsolated RS232 Interface Achieves High Data Rate", Electronics, Vol. 55, No. 1, p. 175, 1982.
 V. G. Oklobdzija, "Improving Testability By Using Additional Circuits", Proceedings of the Seventeenth Asilomar Conference on Circuits, Systems and Computers, pp. 118123, 1983.
 J. P. Roth, V. G. Oklobdzija and J. F. Beetem, "Test Generation For FET Switching Circuits", Proceedings of the International Test Conference, pp. 5962, 1984.
 V. G. Oklobdzija and P. G. Kovijanic, "On Testability Of CMOSDomino Logic", Proceedings FTCS14 : 14th IEEE International Conference on Fault Tolerant Computing, pp. 5055, 1984.
 V. G. Oklobdzija and E. R. Barnes, "Some Optimal Schemes For ALU Implementation In VLSI Technology", Proceedings of the 7th Symposium on Computer Arithmetic ARITH7, pp. 28. Reprinted in Computer Arithmetic, E. E. Swartzlander, (editor), Vol. II, pp. 137142, 1985.
 V. G. Oklobdzija and R. K. Montoye, "DesignPerformance TradeOffs In CMOS Domino Logic", Proceedings of the Custom Integrated Circuits Conference, pp. 334337, 1985.
 V. G. Oklobdzija and R. K. Montoye, "DesignPerformance TradeOffs In CMOSDomino Logic", IEEE Journal of Solid State Circuits, Vol. SC21, No. 2, pp. 304306, 1986.
 V. G. Oklobdzija, N. M. Marinovic and L. Roytman, "SingleChip Architecture For RealTime Computation Of The Wigner Distribution Of Acoustic Signals", Proceedings of the 21st Asilomar Conference on Signals, Systems and Computers, pp. 939943, 1987.
 V. G. Oklobdzija and E. R. Barnes, "On Implementing Addition in VLSI Technology", IEEE Journal of Parallel and Distributed Computing, No. 5, pp. 716728, 1988.
 V. G. Oklobdzija, "Architecture For SingleChip ASIC Processor With Integrated Floating Point Unit", Proceedings of the 21st Hawaii International Conference on System Sciences, pp. 19, 1988. (Best Paper award)
 V. M. Marinovic, V. G. Oklobdzija and L. Roytman, "VLSI Architecture Of A RealTime Wigner Distribution Processor For Acoustic Signals", Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, V4.7, pp. 21122115, 1988.
 V. G. Oklobdzija and G. Grohosky, "Architectural Study For An Integrated Fixed And FloatingPoint VLSIASIC Processor", COMPEURO'88, IEEE Symposium on Circuits and Systems, pp. 108115, 1988.
 V. G. Oklobdzija, "Simple And Efficient CMOS Circuit For Fast VLSI Adder Realization", Proceedings of the International Symposium on Circuits and Systems, pp. 14, 1988.
 V. G. Oklobdzija, "Issues In CPUCoprocessor Communication And Synchronization", EUROMICRO '88, Fourteenth Symposium, Microprocessing and Microprogramming, NorthHolland Publishers, Vol. 24, pp. 695700, 1988.
 V. G. Oklobdzija, "Rapid TurnAround Design Style And Technology: Impact On Computer Architecture", Proceedings of the 22nd Annual Hawaii International Conference on System Sciences (HICSS22), Vol. 1, page 1, 1989.
1990 to 1994
 B. D. Lee and V. G. Oklobdzija, "Optimization And Speed Improvement Analysis Of CarryLookahead Adder Structure", Proceedings of the 24th Asilomar Conference on Signals, Systems and Computers, Vol. 2 of 2, pp. 918922, 1990.
 P. K. Chan, M. D. F. Schlag, C. D. Thomborson and V. G. Oklobdzija, "Delay Optimization Of CarrySkip Adders And Block CarryLookahead Adders", Proceedings of the 10th IEEE Symposium on Computer Arithmetic, ARITH10, pp. 111, 1991.
 B. D. Lee and V. G. Oklobdzija, "Improved CLA Scheme With Optimized Delay", Journal of VLSI Signal Processing, Vol. 3, No. 4, pp. 265274, 1991.
 A. Sah, D. C. Verma and V. G. Oklobdzija, "A Study Of I/O Architecture For High Performance Next Generation Computers", Proceedings of the 2nd Symposium on High Performance Computing, pp. 112, 1991.
 N. M. Marinovic and V. G. Oklobdzija, "VLSI Chip Architecture For RealTime Ambiguity Function Computation", Proceedings of the 25th Asilomar Conference on Signals, Systems and Computers, 1991, 5 pages.
 P. K. Chan, M. D. Schlag, C. D. Thomborson and V. G. Oklobdzija, "Delay Optimization Of CarrySkip Adders And Block CarryLookahead Adders Using Multidimensional Dynamic Programming", IEEE Transactions on Computers, Vol. 41, No. 8, pp. 920930, 1992.
 V. G. Oklobdzija, "An Implementation Algorithm And Design Of A Novel Leading Zero Detector Circuit", 26th IEEE Asilomar Conference on Signals, Systems and Computers, Vol 1, pp. 391395, 1992. (Invited paper)
 V. G. Oklobdzija, D. Villeger, and T. Soulas, "Considerations For Design Of A Complex Multiplier", 26th IEEE Asilomar Conference on Signals, Systems and Computers, Asilomar, Vol. 1, pp. 366370, 1992. (Invited paper)
 V. G. Oklobdzija, "Algorithmic Design Of A Hierarchical And Modular Leading Zero Detector Circuit", Electronics Letters, Vol. 29, No. 3, pp. 283284, 1992.
 T. Soulas, D. Villeger and V. G. Oklobdzija, "An ASIC Macro Cell Multiplier For Complex Numbers", Proceedings of EUROASIC93, the European (EDAC) Conference in ASIC Design, 1993, 5 pages.
 V. G. Oklobdzija, "Computer Arithmetic", The Electrical Engineering Handbook, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., pp. 18581865, 1993.
 V. G. Oklobdzija and D. Villeger, "Multiplier Design Utilizing Improved Column Compression Tree And Optimized Final Adder In CMOS Technology", Proceedings of the 1993 International Symposium on VLSI Technology, Systems and Applications, pp. 209212, 1993.
 V. G. Oklobdzija, "A Hierarchical And Modular Circuit Implementing Leading Zero Detector For A HighPerformance FloatingPoint Processor", Proceedings of the 5th International Symposium on IC Technology, Systems, and Applications, ISIC93, Nanyang Technological University, Singapore, 1993, 2 pages.
 V. G. Oklobdzija, D. Villeger, and T. Soulas, "An Integrated Multiplier For Complex Numbers", Journal of VLSI Signal Processing, Vol. 7, No. 3, pp. 213222, 1993.
 V. G. Oklobdzija, "An Algoritmic And Novel Design Of A Leading Zero Detector Circuit: Comparison With Logic Synthesis", IEEE Transactions on VLSI Systems, Vol. 2, No. 1, pp. 124128, 1993.
 D. Villeger and V. G. Oklobdzija, "Analysis Of Booth Encoding Efficiency In Parallel Multipliers Using Compressors For Reduction Of Partial Products", Proceedings of the 27th Asilomar Conference on Signals, Systems and Computers, pp. 781784, 1993.
 D. Villeger and V. G. Oklobdzija, "Evaluation Of Booth Encoding Techniques For Parallel Multiplier Implementation", Electronics Letters, Vol. 29, No. 23, pp. 20162017, 1993.
 V. G. Oklobdzija, "New ECL Gate In BiFET Process", Electronics Letters, Vol. 29, No. 23, pp. 20292030, 1993.
 M. Q. Le and V. G. Oklobdzija, "Logic Synthesis For ASIC: A Guided Algorithmic Approach", Proceedings of the 1994 International Conference on ASIC, 1994, 4 pages.
 A. de la Serna, M. A. Soderstrand and V. G. Oklobdzija, "System For Rapid Prototyping Of Application Specific Signal Processors For ASIC Implementation", Proceedings of the 1994 International Conference on ASIC Implementation, pp. 157160, 1994.
 R. Hundal and V. G. Oklobdzija, "Determination Of Optimal Sizes For A First And Second Level SRAMDRAM OnChip Cache Combination", Proceedings of the 1994 International Conference on Computer Design, 1994, 5 pages.
 V. G. Oklobdzija, "An ECL Gate With Improved Speed And Low Power In BiCMOS Process", Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting, 1994, 4 pages.
 V. G. Oklobdzija, "Design And Analysis Of Fast CarryPropagate Adder Under NonEqual Input Signal Arrival Profile", Proceedings of the 28th Asilomar Conference on Signals, Systems and Computers, 1994, 4 pages.
 R. H. Strandberg, J. C. Le Duc, ZY. Yang, L. G. Bustamante, V. G. Oklobdzija and M. Soderstrand, "Reconfigurable Processor For RealTime Adaptive Sample Rate Notch Filtering", Proceedings of the 28th Asilomar Conference on Signals, Systems and Computers, 1994, 4 pages.
 R. H. Strandberg, J. C. Le Duc, L. G. Bustamante, V. G. Oklobdzija, and M. Soderstrand, "Implementation Of Adapative Sample Rate KwanMartin Notch Filter Using Efficient Realizations Of Reciprocal And Squaring Circuit", Proceedings of the 28th Asilomar Conference on Signals, Systems and Computers, 1994, 5 pages.
1995 to 1999
 V. G. Oklobdzija and D. Villeger, "Improving Multiplier Design By Using Improved Column Compression Tree And Optimized Final Adder In CMOS Technology", IEEE Transactions on VLSI Systems, Vol. 3, No. 2, June, 1995, 10 pages.
 V. G. Oklobdzija, "Computer Organization: Architecture", The Engineering Handbook, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., 1995, 20 pages.
 M. N. Dorojevets and V. G. Oklobdzija, "Multithreaded Decoupled Architecture", International Journal of HighSpeed Computing, World Scientific Publisher, 16 pages, June, 1995.
 V. G. Oklobdzija, D. Villeger, and S. S. Liu, "A Method For Speed Optimized Partial Product Reduction And Generation Of Fast Parallel Multipliers Using An Algorithmic Approach", IEEE Transactions on Computers, Vol. 45, No. 3, March 1996.
 K. J. Runge, P. Lee, J. Correa, R.T. Scalettar, V.G. Oklobdzija, "Monte Carlo and Molecular Dynamic Simulations Using P4", Proceedings of the 9th Int'l Parallel Processing Symposium, Santa Barbara, California, April 2429, 1995, 7 pages.
 D. Maksimovic, V.G. Oklobdzija, "Integrated Power Clock Generators for Low Energy Logic", Proceedings of the 1995 Power Electronics Specialists Conference, Atlanta, Georgia, June 1822, 1995.
 V. G. Oklobdzija and B. Duchene, "PassTransistor Dual Value Logic For LowPower CMOS", Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31June 2nd, 1995.
 C. Martel, V. G. Oklobdzija, R. Ravi and P. Stelling, "Design Strategies For Optimal Multiplier Circuits", Proceedings of the 12th IEEE Symposium on Computer Arithmetic, Bath, ENGLAND, July 1921,1995, 8 pages.
 V. G. Oklobdzija, "Computers", The Engineering Handbook, R. C. Dorf (Ed.), Introduction into Computers, a Chapter, CRC Press, Inc., 1995, 20 pages.
 V. G. Oklobdzija, "An ECL Gate with Improved Speed And LowPower in BiCMOS Process", Journal of Solid State Circuits, January 1996.
 V. G. Oklobdzija and B. Duchene, "Logic Synthesis For PassTransistor Design", IEEE International Conference on SolidState and IntegratedCircuit Technology, October 2428, 1995, Beijing, China.
 V. G. Oklobdzija and B. Duchene, "PassTransistor Logic Family for HighSpeed and Low Power CMOS", Sixth International Symposium on IC Technology, Systems and Applications, ISIC95, Singapore, September 68, 1995.
 D. Maksimovic, V. G. Oklobdzija, "Clocked CMOS Adiabatic Logic with Single AC Power Supply", 21st European SolidState Circuits Conference, September 1921, 1995, Lille, FRANCE.
 V. G. Oklobdzija, "Digital Systems", The Engineering Handbook, R. C. Dorf (Ed.), Introduction into Digital Systems, Chapter, in press, CRC Press, Inc., 1995.
 V. G. Oklobdzija and B. Duchene, "Development and Synthesis Method for PassTransistor Logic Family for HighSpeed and Low Power CMOS", 38th Midwest Symposium on Circuits and Systems, Rio de Janeriro, BRASIL, Auguts 1316, 1995.
 K. J. Runge, P. Lee, J. Correa, R. T. Seabettar, and V. G. Oklobdzija, "Simulations of Interacting Many Body Systems Using P4", Journal of HighSpeed Computing, World Scientific Publisher, 27 pages, August 1995.
 P. Bonatto, V. G. Oklobdzija, "Evaluation of Booth's Algorithm for Implementation in Parallel Multipliers", TwentyNinth Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29  November 1, 1995.
 Jean Noel, V. G. Oklobdzija, "New Pipelined Architecture for DSP", TwentyNinth Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29  November 1, 1995.
 V. G. Oklobdzija, P. Stelling, "Design Strategies for the Final Adder in a Parallel Multiplier", TwentyNinth Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29  November 1, 1995.
 V. G. Oklobdzija, "A Method for Generation of Fast Parallel Multipliers", 2nd International Conference on Massively Parallel Computing Systems, May 69, 1996, Ischia, ITALY.
 K. W. Current, V. G. Oklobdzija, D. Maksimovic, "LowEnergy Logic Circuit Techniques for Multiple Valued Logic", Second Int'l Symposium on MultipleValued Logic, Santiago de Compostela, Spain, May 2931, 1996.
 P. Stelling , V. G. Oklobdzija, "Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier", special issue on VLSI Arithmetic, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol. 14, No. 3, December 1996.
 R.H. Strandberg, JC Le Duc, L.G. Bustamante, V. G. Oklobdzija, M. Soderstrand, "Efficient Realization of Squaring Circuit and Reciprocal used in Adaptive Sample Rate Notch Filters", special issue on VLSI Arithmetic, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol. 14, No. 3, December 1996.
 V. G. Oklobdzija, Comments on "LeadingZero Anticipatory Logic for HighSpeed Floating Point Addition", IEEE Journal of SolidState Circuits, Vol. 32, No. 2, pp. 292293, February 1997.
 P. Stelling, V. G. Oklobdzija, "Implementing MultiplyAccumulate Operation in Multiplication Time", Thirteenth International Symposium on Computer Arithmetic, Pacific Grove, California, July 5  9, 1997.
 D. Maksimivic, V. G. Oklobdzija, B. Nikolic, K. W. Current, "Design and Experimental Verification of a CMOS Adiabatic Logic with SinglePhase PowerClock Supply", Proceedings of the 40th Midwest Symposium on Circuits and Systems, Sacramento, California, August 36, 1997.
 D. Maksimovic, V. G. Oklobdzija, B. Nikolic, K. W. Current, "Clocked CMOS Adiabatic Logic with Integrated SinglePhase PowerClock Supply: Experimental Results", International Symposium on Low Power Electronics and Design, Monterey, California, August 1820, 1997.
 Paul F. Stelling and Vojin G. Oklobdzija, "Optimal Designs for Multipliers and MultiplyAccumulators", Proceedings of the 15th IMACS World Congress on Scientific Computation, Modeling, and Applied Mathematics, Volume 4 Artificial Intelligence and Computer Science, Achim Sydow, editor, Wissenschaft and Technik Verlag, Berlin, August 1997, pp. 739744.
 B. Nikolic, V. G. Oklobdzija, "A SinglePhase Clock HighPerformance BiCMOS Latch", Proceedings of the 7th International Symposium on IC Technology, Systems & Applications, Singapore, September 1012, 1997.
 K. W. Current, V. G. Oklobdzija, D. Maksimovic, "On Adiabatic Multiple Valued Logic Circuits", Journal of Multiple Value Logic, Vol. 2, Gordon and Breach Publishing, pp. 329347, 1997.
 V. G. Oklobdzija, "Differential and PassTransistor CMOS Logic for HighPerformance Systems", 21st International IEEE Conference on Microelectronics, September 1417, 1997, Nis, Yugoslavia.
 V. G. Oklobdzija, D. Maksimovic, F. C. Lin, "PassTransistor Adiabatic Logic using Single PowerClock Supply", IEEE Transactions on Circuits and SystemsII, Vol. 44, No. 10, pp. 842846. October 1997.
 V. G. Oklobdzija and B. Duchene, "Synthesis Of HighSpeed PassTransistor Logic", IEEE Transactions on Circuits and SystemsII, Vol. 44, No. 11, November 1997, 7 pages.
 V. G. Oklobdzija, "Differential and PassTransistor CMOS Logic for HighPerformance Systems", reprinted from 21st International IEEE Conference on Microelectronics, Electronics, Vol. 1, No. 1, December 1997.
 V. G. Oklobdzija, "Differential and PassTransistor CMOS Logic for HighPerformance Systems", Microelectronics Journal, Elsevier Publishing, March 1998.
 P. Stelling, C. Martel, V. G. Oklobdzija, R. Ravi, "Optimal Circuits For Parallel Multipliers", IEEE Transactions on Computers, Vol. 47, No. 3, pp. 273285, March 98.
 A. A. Farooqui, V. G. Oklobdzija, "General DataPath Organization of a MAC unit for VLSI Implementation of DSP Processors", 1998 IEEE International Symposium on Circuits and Systems, Monterey, California, May 31  June 3, 1998.
 B. Nikolic, V. G. Oklobdzija, "Low Voltage BiCMOS TSPC Latch for High Performance Digital Systems", 1998 IEEE International Symposium on Circuits and Systems, May 31  June 3, 1998, Monterey, California.
 V. G. Oklobdzija, "Architectural Tradeoffs for Low Power", International Symposium on Computer Architecture, Barcelona, SPAIN, June 27July 1st, 1998.
 V. Stojanovic, V. G. Oklobdzija, R. Bajwa, "A Unified Approach in the Analysis of Latches and FlipFlops for LowPower Systems", International Symposium on Low Power Electronics and Design, Monterey, California, August 1012, 1998.
 V. Stojanovic, V. G. Oklobdzija, R. Bajwa, "Comparative Analysis of Latches and FlipFlops for HighPerformance Systems", International Conference on Computer Design, Austin, Texas, October 57, 1998.
 A. A. Farooqui, V. G. Oklobdzija, "Early Branch Prediction Circuit For High Performance Digital Signal Processors", 1998 IEEE Conference on Microelectronics, Monastir, Tunisia, December 1416, 1998.
 B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, M. Leung, "Sense AmplifierBased FlipFlop", 1999 IEEE International SolidState Circuits Conference, San Francisco, February 1999.
 V. Stojanovic and V. G. Oklobdzija, "Comaparative Analysis of MasterSlave Latches and FlipFlops for HighPerformance and LowPower Systems", IEEE Journal of SolidState Circuits, Vol. 34, No. 4, April 1999.
 V. G. Oklobdzija, "Digital Arithmetic", Wiley Encyclopedia of Electrical and Electronics Engineering, Vol. 5, Book Chapter, John Wiley publishing, 1999.
 V. G. Oklobdzija, "Reduced Instruction Set Computing", Wiley Encyclopedia of Electrical and Electronics Engineering, Vol. 18, Book Chapter, John Wiley publishing, 1999.
 A. Farooqui, V. G. Oklobdzija, "VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing", 9th Great Lakes VLSI conference (GLSVLSI 99), Ann Arbor, Michigan, March 46, 1999.
 A. Farooqui, V. G. Oklobdzija, F. Chehrazi, "64Bit Media Adder", 1999 IEEE International Symposium on Circuits and Systems, Orlando, Florida, May 58, 1999.
 A. Farooqui, V. G. Oklobdzija, F. Chehrazi, "Multiplexer Based Adder for Media Signal Processing", 1999 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, June 810, 1999.
 B. Nikolic, V. G. Oklobdzija, "Design and Optimization of Sense AmplifierBased FlipFlops", 25th European SolidState Circuits Conference, Duisburg, GERMANY, 2123 September 1999.
 F. Chehrazi, V. G. Oklobdzija, A. A. Farooqui, "SingleCycle Throughput MultiMedia Multiplier", SONY Research Forum (SRF), Tokyo, JAPAN, October 1999.
 B. Nikolic, M. Leung, L. Fu, V.G. Oklobdzija, R. Yamasaki, "ReducedComplexity Sequence Detection for E^{2}PR4 Magnetic Recording Channel", Proceedings of Global Telecommunications Conference, Globcom '99, Rio de Janeiro, BRAZIL, December 1999.
2000 to 2004
 D. Markovic, B. Nikolic, V.G. Oklobdzija, "General Method in Synthesis of PassTransistor Circuits", 22nd International IEEE Conference on Microelectronics, May, 2000, Nis, Yugoslavia.
 B. Nikolic, V. G. Oklobdzija, V. Stojanovic, W. Jia, J. Chiu, M. Leung, "Improved Sense AmplifierBased FlipFlop: Design and Measurements", IEEE Journal of SolidState Circuits, Vol. 35, No. 6, June 2000.
 V. G. Oklobdzija, A. A. Farooqui, "Computer Arithmetic for the Processing of Media Signals", Invited Paper, Proceedings of SPIE Vol. 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations, San Diego, California, USA, 2 4 August, 2000.
 D. Maksimovic, V. G. Oklobdzija, B. Nikolic, K. W. Current, "Clocked CMOS Adiabatic Logic with Integrated SinglePhase PowerClock Supply", IEEE Transactions on VLSI Systems, Vol. 8, No. 4, August 2000.
 A. Farooqui, K. W. Current, V. G. Oklobdzija, "Partitioned Branch Condition Resolution Logic", Proceedings of the Symposium on Integrated Circuits and Systems Design, SBCCI2000, Manaus, Brazil, September 1822, 2000.
 N. Nedovic, V. G. Oklobdzija, "Hybrid Latch FlipFlop with Improved Power Efficiency", Proceedings of the Symposium on Integrated Circuits and Systems Design, SBCCI2000, Manaus, Brazil, September 1822, 2000.
 N. Nedovic, V. G. Oklobdzija, "Dynamic FlipFlop with Improved Power", Proceedings of the 26th European SolidState Circuits Conference, ESSCIRC 2000, Stockholm, Sweden, September 1921, 2000.
 N. Nedovic, V. G. Oklobdzija, "Dynamic FlipFlop with Improved Power", Proceedings of the International Conference on Computer Design, ICCD 2000, Austin, Texas, September 1820, 2000.
 A. Farooqui, V. G. Oklobdzija, "Impact of Architecture Extensions for Media Signal Processing on DataPath Organization", 34th Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29  November 1, 2000.
 A. Farooqui, V. G. Oklobdzija, "A Programmable DataPath for MPEG4 and Natural Hybrid Video Coding", 34th Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29  November 1, 2000.
 V. G. Oklobdzija, "Computational Requirements for Media Signal Processing", 34th Annual Asilomar Conference on signals, Systems and Computers, Pacific Grove, California, October 29  November 1, 2000.
 D. Markovic, B. Nikolic, V.G. Oklobdzija, "General Method in Synthesis of PassTransistor Circuits", Microelectronics Journal, Elsevier Science Publishing, No. 31, NovemberDecember, 2000, p.991998.
 A. Inoue, V. G. Oklobdzija, W. W. Walker, M. Kai, T. Izawa, "A Low Power SOI Adder Using ReducedSwing Charge Recycling Circuits", 2001 IEEE International SolidState Circuits Conference Digest of Technical papers, San Francisco, February 2001.
 N. Nedovic, V. G. Oklobdzija, M. Leung, "FIR Filter for Adaptive Equalization in PRML Read Channels", The 5th World MultiConference on Systemics, Cybernetics and Informatics SCI 2001, Orlando, Florida, July 2225, 2001.
 H. Q. Dao, K. Nowka, V. G. Oklobdzija, "Analysis of Clocked Timing Elements for DVS Effects over Process Parameter Variation", Proceedings of the International Symposium on Low Power Electronics and Design, Huntington Beach, California, August 67, 2001.
 N. Nedovic, M. Aleksic, V. G. Oklobdzija, "Conditional Techniques for Low Power Consumption FlipFlops", Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems, Malta, September 25, 2001.
 N. Nedovic, M. Aleksic, V. G. Oklobdzija, "Timing Characterization of DualEdge Triggered FlipFlops", Proceedings of the International Conference on Computer Design, ICCD 2001, Austin, Texas, September 2326, 2001.
 H. Q. Dao, V. G. Oklobdzija, "Application of Logical Effort on Delay Analysis of 64bit Static CarryLookahead Adder", 35th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, November 47, 2001.
 X. Y. Yu, V. G. Oklobdzija, W. W. Walker, "Application of Logical Effort on Design of Arithmetic Blocks", 35th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, November 47, 2001.
 H. Q. Dao, V. G. Oklobdzija, "Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders", 35th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, November 47, 2001
 C. Cuche, C. Piguet, V. G. Oklobdzija, "Design Flow and CAD Tools for Asynchronous Design of Sequential Library Cells", Second Working Group on Asynchronous Circuit Design (ACiDWG) Workshop of the European Commission's Fifth Framework Programme, Munich, Germany, 2829 January, 2002.
 M. SaintLaurent, V. G. Oklobdzija, S. S. Singh, M. Swaminathan, J. D. Meindl, "Optimal Sequencing Energy Allocation for CMOS Integrated Systems", 3rd International Symposium on Quality Electronic Design, San Jose, California, March 1820, 2002.
 V. G. Oklobdzija, "Clocking in MultiGHz Environment", 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595). IEEE. Part vol.2, 2002, pp. 5618 vol.2. Piscataway, NJ, USA.
 V. G. Oklobdzija, "Clocking in MultiGHz Environment", Electrical Engineering Series, Facta Universitatis, Nis, Vol. 15, No. 1. April 2002. (reprint from 23rd International Conference on Microelectronics. Proceedings, 2002)
 N. Nedovic, M. Aleksic, V. G. Oklobdzija, "Comparative Analysis of DoubleEdge versus SingleEdge Triggered Clocked Storage Elements", 2002 IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, May 2629, 2002.
 N. Nedovic, M. Aleksic, V. G. Oklobdzija, "Conditional PreCharge Techniques for PowerEfficient DualEdge Clocking", Proceedings of the International Symposium on LowPower Electronics and Design, Monterey, California, August 1214, 2002.
 V. G. Oklobdzija, J. Sparso, "Future Directions in Clocking MultiGHz Systems", ISLPED'02: Proceedings of the 2002 International Symposium on Lower Power Electronics and Design (IEEE Cat. No.02TH8643). ACM. 2002, pp. 219. New York, NY, USA.
 H. Q. Dao, V. G. Oklobdzija, "Performance Comparison of VLSI Adders Using Logical Effort", 12^{th} International Workshop on Power And Timing Modeling, Optimization and Simulation, Sevilla, SPAIN, September 1113, 2002.
 V. G. Oklobdzija, "Clocking and Clocked Storage Elements in MultiGHz Environment", Invited paper, 12^{th} International Workshop on Power And Timing Modeling, Optimization and Simulation, Sevilla, SPAIN, September 1113, 2002.
 N. Nedovic, W. W. Walker, V. G. Oklobdzija, M. Aleksic, "A Low Power Symmetrically Pulsed Dual EdgeTriggered FlipFlop", Proceedings of the 28^{th} European SolidState Circuits Conference, Florence, ITALY, September 2426, 2002.
 N. Nedovic, V. G. Oklobdzija, W. W. Walker, "A Clock Skew Absorbing FlipFlop", 2003 IEEE International SolidState Circuits Conference Digest of Technical papers, San Francisco, February 2003.
 A. A. Farooqui, V. G. Oklobdzija, S. M. Sait, "AreaTime Optimal Adder with Relative Placement Generator", International Symposium on Circuits and Systems, Bangkok, Thailand, May 2528, 2003.
 X. Y. Yu, V. G. Oklobdzija, W. W. Walker, "An Efficient Transistor Optimizer for Custom Circuits", International Symposium on Circuits and Systems, Bangkok, Thailand, May 2528, 2003.
 B. R. Zeydel, V.G. Oklobdzija, S. Mathew, R.K. Krishnamurthy, S. Borkar, "A 90nm 1GHz 22mW 16x16bit 2's Complement Multiplier for Wireless Baseband", Proceedings of the 2003 Symposium on VLSI Circuits, Kyoto, JAPAN, June 12  14, 2003.
 V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, R. Krishnamurthy, "EnergyDelay Estimation Technique for HighPerformance Microprocessor VLSI Adders", Proceedings of the International Symposium on Computer Arithmetic, ARITH16, Santiago de Compostela, SPAIN, June 1518, 2003
 H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy Minimization Method for Optimal EnergyDelay Extraction", Proceedings of the European SolidState Circuits Conference, ESSCIRC 2003, Estoril, PORTUGAL, September 1618, 2003.
 H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy Optimization of HighPerformance Circuits", Proceedings of the 13th International Workshop on Power And Timing Modeling, Optimization and Simulation, Torino, Italy, September 1012, 2003.
 V. G. Oklobdzija, "Clocking and Clocked Storage Elements in a MultiGigahertz Environment", IBM Journal of Research and Development, Vol. 47, No. 5/6, pp. 567584, September/November 2003.
 V. G. Oklobdzija, "MultiGHz Systems Clocking", Invited Paper, Proceedings of the 5th International Conference on ASIC, Beijing, P.R. China, October 2224, 2003.
 V. G. Oklobdzija, "Issues in System on the Chip Clocking", Invited Paper, Proceedings of the IEEK System on Chip Design Conference, Seoul, Korea, November 56, 2003.
 M. Vratonjic, B. R. Zeydel, H. Q. Dao, V. G. Oklobdzija, "LowPower Aspects of Different Adder Topologies", 37th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, November 912, 2003.
 N. Nedovic, W. W. Walker, V. G. Oklobdzija, "A Test Circuit for Measurement of Clocked Storage Element Characteristics", IEEE Journal of SolidState Circuits, Vol. 39, No. 8, pp. 12941304, August 2004.
2005  2010
 H. Q. Dao, B. R. Zeydel, V. Zyuban, V. G. Oklobdzija, "A Method for Energy Optimization of Digital Pipelined Systems", The Fourth Annual IBM Austin Conference on EnergyEfficient Design, ACEED 2005, Austin, Texas, March 13, 2005.
 N. Nedovic, V. G. Oklobdzija, "DualEdge Triggered Storage Elements and Clocking Strategy for LowPower Systems", IEEE Transaction on VLSI Systems, Volume 13, Issue 5, pp. 577590, May 2005.
 V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, R. Krishnamurthy, "Comparison of HighPerformance VLSI Adders in EnergyDelay Space", IEEE Transaction on VLSI Systems, Volume 13, Issue 6, pp. 754758, June 2005.
 B.R. Zeydel, T.T.J.H. Kluter, V. G. Oklobdzija, "Efficient EnergyDelay Mapping of Addition Recurrence Algorithms in CMOS", International Symposium on Computer Arithmetic, ARITH17, Cape Cod, Massachusetts, USA, June 2729, 2005.
 M. Aleksic, N. Nedovic, K. W. Current, V. G. Oklobdzija, "A New Model for Timing Jitter Caused by Device Noise in CurrentMode Logic Frequency Dividers", in Proc. of the 15th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Leuven, Belgium, September 2123, 2005.
 H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Architectural Considerations for Energy Efficiency", Proceedings of the International Conference on Computer Design, ICCD 2005, San Jose, California, October 25, 2005.
 M. Vratonjic, B. R. Zeydel, V. G. Oklobdzija, "Low and Ultra LowPower Arithmetic Units: Design and Comparison", Proceedings of the International Conference on Computer Design, ICCD 2005, San Jose, California, October 25, 2005.
 H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "EnergyEfficient Optimization of the Viterbi ACS Unit Architecture", Proceedings of the Asian SolidState Circuit Conference, ASSCC 2005, Hsinchu, Taiwan, November 13, 2005.
 S. K. Hsu, S. K. Mathew, M. A. Anders, B. R. Zeydel, V. G. Oklobdzija, R. K. Krishnamurthy, S. Y. Borkar, "A 110 GOPS/W 16bit Multiplier and Reconfigurable PLA Loop in 90nm CMOS", IEEE Journal of SolidState Circuits, Vol. 41, No. 1, pp. 256264, January 2006.
 H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy Optimization of Pipelined Digital Systems Using Circuit Sizing and Supply Scaling", IEEE Transaction on VLSI Systems,Vol. 14, Issue 2, Feb. 2006 pp. 122134.
 C. Giacomotto, N. Nedovic, V. G. Oklobdzija, "EnergyDelay Space Analysis for Clocked Storage Elements under Process Variations", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 1315, 2006.
 B. R. Zeydel, V. G. Oklobdzija, "Methodology for EnergyEfficient Digital Circuit Sizing: Important Issues and Design Limitations", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 1315, 2006.
 M. Vratonjic, B. R. Zeydel, V. G. Oklobdzija, "Circuit Sizing and SupplyVoltage Selection for LowPower Digital Circuit Design", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 1315, 2006.
 X. Y. Yu, R. Montoye, K. Nowka, B. Zeydel, V. Oklobdzija, "Circuit Design Style for Energy Efficiency: LSDL and Compound Domino", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 1315, 2006.
 C. Giacomotto, N. Nikola, V. Oklobdzija, "The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements", IEEE Journal of SolidState Circuits, Vol. 42, No. 6, pp. 13921404, June 2007.
 M. Singh, C. Giacomotto, B. R. Zeydel, V. Oklobdzija, "Logic Style Comparison for Ultra Low Power Operation in 65nm Technology", 17th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Gothenburg, Sweden Sept. 35, 2007 .
 C. Giacomotto, M. Singh, M. Vratonjic, V. Oklobdzija, "Energy Efficiency of PowerGating in LowPower Clocked Storage Elements", 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal Sept. 1012, 2008
.
 M. Aleksic, K.
W. Current, V. G. Oklobdzija,
"Jitter Analysis of NonAutonomous MOS CurrentMode Logic Circuits"
IEEE Transaction on Circuits and Systems I, Special Issue, Vol.
55, No.10, November 2008.
 D. Baran, M. Aktan, H. Karimiyan, V. G. Oklobdzija, "Exploration of Switching Activity Behavior of Addition Algorithms", IEEE MWSCAS 2009, Cancun, Mexico, 25 August 2009.
 Joosik Moon, Mustafa Aktan, V. G. Oklobdzija, "Design Methodology for Clocked Storage Elements Robust to Process Variations", CENICS 2009, Sliema, Malta, 1116 October 2009.
 D. Baran, M. Aktan,H. Karimiyan, V. G. Oklobdzija, "Switching Activity Calculation of VLSI Adders", IEEE ASICON 2009, Changsha, China, 2023 October 2009.
 D. Baran, M. Aktan,H. Karimiyan, V. G. Oklobdzija, "Switching Activity Calculation of VLSI Adders", IEEE ASICON 2009, Changsha, China, 2023 October 2009.
 Joosik Moon, Mustafa Aktan, V. G. Oklobdzija, "Clocked Storage Elements Robust to Process Variations", IEEE ASICON 2009, Changsha, China, 2023 October 2009.
 H. K. Alidash, S. M. Sayedi, H. Saidi, and V. G. Oklobdzija, "Soft Error Filtered and Hardened Latch," IEEE ASICON 2009, Changsha, China, 2023 October 2009.
 M. Aktan, S. Paramesvaran, J. Moon, and V. G. Oklobdzija, "EnergyDelay Space Exploration of Clocked Storage Elements Using Circuit Sizing," the Austin conference on Integrated systems and Circuits (ACISC), Austin, 2009.
 H. K. Alidash and V. G. Oklobdzija, "LowPower Soft Error Hardened Latch," PATMOS 2009, 19th international Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Delft, Holland, 2009.
 M. Vratonjic, M. Ziegler, G. D. Gristede, V. Zyuban, T. Mitchell, E. Cho, C. Visweswariah, V. G. Oklobdzija, "A New Methodology for PowerAware Transistor Sizing: Free Power Recovery (FPR)" , PATMOS 2009, 19th international Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Delft, Holland, 2009.
 H. Karimiyan Alidash and V. G. Oklobdzija., "LowPower Soft Error Hardened Latch", Journal Low Power Electronics 6, 218226 (2010).
 B. R. Zeydel, D. Baran, V. G. Oklobdzija, "Energy Efficient Design of HighPerformance VLSI Adders ", IEEE Journal of SolidState Circuits , Vol 45, Issue 6. June 2010.
 Baran, Dursun; Aktan, Mustafa; Oklobdzija, Vojin G.; " Energy efficient implementation of parallel CMOS multipliers with improved compressors," LowPower Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on, pp.147152, 1820 Aug. 2010.
2010  on
 Baran, Dursun; Aktan, Mustafa; Oklobdzija, Vojin G.; "Multiplier Structures for Low Power Applications in DeepCMOS,"
Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS 2011), pp., 1518 May. 2011.
 Aktan, Mustafa; Baran, Dursun; Oklobdzija, Vojin G.; "A Quick Method for Energy Optimized Gate Sizing of Digital Circuits," International Workshop, PATMOS 2011 on Power and Timing Modeling, Optimization, and Simulation, Madrid, SPAIN, September 27, 2011.
 Hossein Karimiyan Alidash, Sayed Masoud Sayedi, Vojin G. Oklobdzija, " SoftError Hardened Redundant Triggered Latch," 4th Asia Symposium on Quality Electronic Design (ASQED), July 1011, 2012.
 V.G. Oklobdzija, M. Aktan, Baran, “Optimal Transistor Sizing and Voltage Scaling for Minimal Energy use at Fixed Performance”, 7^{th} Argentine School of MicroNanoelectronics, Technology and Applications (EAMTA 2012), Cordoba, Argentina, August 412, 2012.
 V. Nawathe, M. Aktan, L. Wang, V. G. Oklobdzija, “Parallelism tradeoffs for datadriven circuits”, 7^{th} Argentine School of MicroNanoelectronics, Technology and Applications (EAMTA 2012), Cordoba, Argentina, August 412, 2012.
Books:
 V. G. Oklobdzija, "HighPerformance System Design: Circuits and Logic", Book, IEEE Press, July, 1999.
 V. G. Oklobdzija, "The Computer Engineering Handbook", CRC Press, December, 2001.
 V. G. Oklobdzija, V. Stojanovic, D. Markovic, N. Nedovic, "Digital System Clocking, HighPerformance and LowPower Aspects", John Wiley, January 2003.
 V. G. Oklobdzija, R. K. Krishnamurthy, "HighPerformance EnergyEfficient Microprocessor Design", Springer, July 2006.
 V. G. Oklobdzija, "Digital Systems and Applications", Taylor & Francis, Nov. 2007.
 V. G. Oklobdzija, "Digital Design and Fabrication", Taylor & Francis, Nov. 2007.
Book Chapters:
 V. G. Oklobdzija, "Digital Arithmetic", Encyclopedia of Electrical Engineering, Vol. 5, John Wiley publishing, pp. 411418, 1998.
 V. G. Oklobdzija, "Reduced Instruction Set Computing", Encyclopedia of Electrical Engineering, Vol. 18, John Wiley publishing, pp. 342351, 1998.
 V. G. Oklobdzija, "Computer Organization: Architecture," The Engineering Handbook, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., pp. 14341446, 1995.
 V. G. Oklobdzija, "Computers", The Engineering Handbook, R. C. Dorf (Ed.), Introduction into Computers, a Chapter, CRC Press, Inc., pp. 14301433, 1995.
 V. G. Oklobdzija, "Digital Systems", The Engineering Handbook, R. C. Dorf (Ed.), Introduction into Digital Systems, CRC Press, Inc., pp. 12861288, 1995.
 V. G. Oklobdzija, "Computer Arithmetic", The Electrical Engineering Handbook, R. C. Dorf (Ed.), a Chapter, CRC Press, Inc., pp. 18581865, 1993.
 V. G. Oklobdzija, "HighSpeed VLSI Arithmetic Units: Adders and Multipliers", in "Design of HighPerformance Microprocessor Circuits", Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000.
 V. G. Oklobdzija, "Clocking MultiGHz Systems", LowPower Electronics Design, C. Piguet (Ed.), a Chapter, CRC Press, Inc, 2004.
 B. R. Zeydel and V. G. Oklobdzija, "Design of energyefficient digital circuits", HighPerformance EnergyEfficient Microprocessor Design, V. G. Oklobdzija and R. K. Krishnamurthy (Eds.), Springer, 2006.
 V. G. Oklobdzija and B. R. Zeydel, "Energydelay characteristics of CMOS adders", HighPerformance EnergyEfficient Microprocessor Design, V. G. Oklobdzija and R. K. Krishnamurthy (Eds.), Springer, 2006.

