Energy-Efficient Circuit Design Project

Circuit designers have ever been exploiting tools to optimize their design.  The typical process is to come up with an initial sizing that satisfy the performance objective and then to feed it to an optimizers to search for the energy-efficient solution.

The most primitive approach is to use the optimization feature of HSPICE [Synopsys].  The Marquardt Scaling Parameter is typically employed.  It uses the Levenberg-Marquardt algorithm to find the actual solution of the optimizing parameters. The search direction for the solution is a combination of the Steepest Descent method and the Gauss-Newton method.  The main problems with this approach are that (a) designers have to manual enter all parameters to optimize and the objective functions, (b) the lengthy process of HSPICE simulation (using non-linear device modeling), and (c) the constant intervention of designers to avoid divergence of the optimization.

The more common approach was to start the design with all minimal gate sizes, then recursively search failed paths and optimize them. Two representatives are TILOS proposed by Fishburn and Dunlop [Fishburn1985] and MINFLOTRANSIT by Sundararajan et al [Sundararajan2000].  These methods use the linear delay modeling of the gates and thus speed up the optimization process.  However, the recursive path search becomes the bottleneck in run time.  In addition, the optimization operates on transistor sizes that increase at least when design complexity grows.

Recently, Zyuban and Strenski proposed the methodology to optimize digital circuits at the micro-architecture and circuit levels [Zyuban2002].  The fundamental goal is to solve the multidimensional optimization problem based on technology characteristics, circuit style, power and performance target, and power supply.  While powerful due to its generality, the method is more applicable to high-level optimization.

Another attempt to optimize circuits is to trade-off some performance for more percentage of energy reduction as proposed by Stojanovic et al [Stojanovic2002] and Brodersen et al [Brodersen2002].  However, this does not resolve the issue of achieving minimal energy for a given delay nor does it give insight into how these lower energy points can be obtained and the associated costs.