Energy-Efficient Circuit Design Project

I. Delay Modeling (.pdf)

Understanding delay characteristic of a gate is fundamental to analyze any digital circuits. In general, the gate delay is nonlinear and depends on so many factors (such as sizing, load, input signal, relative sizing of transistors in the gate, and so on). So, there is no way to get the accurate delay except simulating it at transistor level (with SPICE).

However, the delay characteristics can be somewhat linearized with certain assumptions. One, PMOS and NMOS transistors are sized so that they achieve the same driving capability.  Two, the signal rate at input matches to the resulting rate at the output. Using the RC-network model, it can be shown that (a) delay of a gate is linearly proportional to the load (normalized its input size) and (b) there is an inherited constant delay cost due to gate parasitics. This modeling can then be applied to optimize the delay of a path or even a multi-path circuit network.

As mentioned, the model is valid only in very strict conditions. It's mostly certain that real circuits do not satisfy them. Therefore, some error will result and the actual delay must be obtained with simulation. Nonetheless, the delay model remains useful in helping designers to analyze and optimize their circuits.

Similarly, the energy consumed in a gate can also be linearly modeled.

(1) Most straightforward is the dynamic energy, linearly contributed by load and its parasitics (proportional to the input size of the gate).

(2) Another source of energy consumption is due short-circuit current.  It is also linearly proportional to input size when signal rates of input and output are matched.

(3) Leakage energy is ignored in arithmetic circuits due to their high switching activity.  However, theoretically, it is proportional to input size.

Accurately estimating energy consumed in a circuit is a daunting task, even with the above linear model of gate energy.  The most complicated issue is the switching activity of individual gates. Such activity depends on both switching probability and relative arrival time of input signals. Typical practice assumes fixed values for static paths and dynamic paths -- the latter is higher.  Knowing that, the energy can be formulated and computed.

Using above delay and energy models, a methodology to optimize energy at targeted performance is created.  The initial design is obtained with equal stage-effort sizing. The optimization is done by re-distributing the delay among stages so that least energy is consumed. The consequent cost is the necessary increase of input size.

Similar methodology is obtained for fix-input fix-output energy optimization. It is essentially the energy-delay tradeoff process. The traded delay is distributed among stages to reduce most energy in the circuit.