Energy-Efficient Circuit Design Project

[Brodersen2002] R.W. Brodersen, M.A. Horowitz, D. Markovic, B. Nikolic, V. Stojanovic, “Methods for True Power Minimization,” International Conference on Computer-Aided Design, ICCAD-2002, Digest of Technical Papers, San Jose, CA, November 10-14, 2002, pp. 35-42.

[Chandrakasan2001] A. Chandrakasan, W. J. Bowhill, F. Fox, “Design of High-Performance Microprocessor Circuits”, IEEE Press, 2001.

[Dao2002] Hoang Dao, Vojin G. Oklobdzija, “ Performance Comparison of VLSI Adders Using Logical Effort”, 12^th International Workshop on Power And Timing Modeling, Optimization and Simulation, Sevilla, SPAIN, September 11-13, 2002.

[Farooqui1999] A. Farooqui, V. G. Oklobdzija, F. Chehrazi, "64-Bit Media Adder", 1999 IEEE International Symposium on Circuits and Systems, Orlando, Florida, May 5-8, 1999.

[Fishburn1985J P. Fishburn and A. E. Dunlop, “TILOS: A Posynomial Programming Approach to Transistor Sizing,” in Proceedings of the 1985 International Conference on Computer-Aided Design, pp. 326–328, November 1985.

[Han1987] T. Han, D. A. Carlson, and S. P. Levitan, “VLSI Design of High-Speed Low-Area Addition Circuitry,” Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1987, pp.418-422.

[Harris1999] D. Harris, R.F. Sproull, and I.E. Sutherland, “Logical Effort Designing Fast CMOS Circuits,” Morgan Kaufmann Publishers, 1999.

[Kogge1973] P.M. Kogge, H.S. Stone, “A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations”, IEEE Trans. Computers, Vol. C-22, No. 8, 1973, pp.786-793

[Ling1981] H. Ling, “High Speed Binary Adder”, IBM Journal of Research and Development, Vol.25, No 3, May 1981, pp. 156-166.

[Naffziger1996] Naffziger, S., “A Sub-Nanosecond 0.5 um 64 b Adder Design”, 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, February 8-10, 1996. p. 362–363.

[Naini1992] A. Naini, D. Bearden, W. Anderson, “A 4.5nS 96-b CMOS Adder Design”, in Proceeding CICC, Feb. 1992, pp. 25.5.1–25.5.4.

[Oklobdzija1988] V. G. Oklobdzija, E. R. Barnes, “On Implementing Addition in VLSI Technology,” IEEE Journal of Parallel and Distributed Computing, No. 5, pp. 716-728, 1988.

[Oklobdzija2002] V. G. Oklobdzija, “Modern Microprocessor Development Perspective,” Keynote Address, 25^th Anniversary of the Electrical Engineering Department, University of Banja Luka, Banja Luka, Serbian Republic, December 21, 2002.

[Park2000] J. Park, H. C. Ngo, J. A. Silberman, S. H. Dhong, “470ps 64-Bit Parallel Binary Adder,” Digest of Technical Papers: 2000 Symposium on VLSI Circuits, 15-17 June 2000

[Stojanovic2002] V. Stojanovic, D. Markovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, “Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Optimization,” Proceedings of the 28^th European Solid-State Circuits Conference, ESSCIRC'2002, Florence, Italy, September 24-26, 2002. pp. 211-214.

[Sundararajan2000] V. Sundararajan, S. S. Sapatnekar, K. K. Parhi, “MINFLOTRANSIT: Min-Cost Flow Based Transistor Sizing Tool,” Design Automation Conference, 2000. Proceedings 2000. 37th, pp. 649–654, June 5-9, 2000

[Sutherland1991] I.E. Sutherland and R.F. Sproull, “Logical Effort: Designing for Speed on the Back of an Envelope”, in C.H. Sequin, Ed., Advanced Research in VLSI. Cambridge, MA: MIT Press, 1991.

[Synopsys] HSPICE Manual, Synopsis Inc.

[Yu2003] Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker, “An Efficient Transistor Optimizer for Custom Circuits,” International Symposium on Circuits and Systems, May 25-28, 2003, Bangkok, Thailand, 2003.

[Zyuban2002] V. Zyuban, and P. Strenski, “Unified Methodology for Resolving Power-Performance Tradeoffs at the Micro-achitectural and Circuit Levels,” IEEE Symposium on Low Power Electronics and Design, 2002.