Energy-Efficient Circuit Design Project

As sub 100nm technologies become feasible for VLSI designs, the notion of energy efficiency has taken on new meaning. In previous technologies energy saving was commonly opportunistic, performed after the target performance was reached. However, in current technologies energy has moved to the forefront of design constraints due to increased battery life desire for mobile systems and power and current density issues seen in high-performance systems. Existing techniques for energy reduction to address these problems focus on modifying operating points in a process, ranging from static and dynamic variation of voltage to static and dynamic variation of threshold voltages. While these approaches achieve savings, they have some drawbacks: on-chip overhead and precision issues associated with dynamic variation; reduced reliability; and in some cases increase sensitivity to process variation. As a result the benefit of such schemes is limited, and appears to be decreasing as technology scales.

Other techniques for reducing energy involves transistor sizing, gate selection, function unit selection, pipeline design, and system architecture. The interdependence of these factors is commonly simplified to treat each item separately due to the complexity involved in the analysis. As a result many opportunities for energy reduction often go unnoticed.

The Energy-Efficient Circuit Design Project focuses on developing techniques which allow for the realization of energy savings associated with transistor sizing, gate selection, functional unit selection, pipeline design, and system architecture. These techniques are designed to be applicable for use in tools as well as by hand, to provide a solution for both designers and improve current CAD flows.

Initial work in energy optimization of functional units demonstrates the potential for 50% energy savings at equal performance for a design or 1FO4 improvement in delay for equal energy. Traditional implementations of adders have shown over a 4x energy penalty compared to energy-efficient implementations of the same adder. Current work is focused on addressing the issues with functional unit selection associated with pipeline optimization.