Energy-Efficient Circuit Design Project

Publications

1. B.R. Zeydel, T.T.J.H. Kluter, V. G. Oklobdžija, "Efficient Mapping of Addition Recurrence Algorithms in CMOS", International Symposium on Computer Arithmetic, ARITH-17, Cape Cod, Massachusetts, USA, June 27-29, 2005

2. V. G. Oklobdžija, B. R. Zeydel, H. Q. Dao, S. Mathew, R. Krishnamurthy, "Comparison of High-Performance VLSI Adders in Energy-Delay Space", IEEE Transaction on VLSI Systems, Volume 13, Issue 6, pp. 754-758, June 2005.

3. H. Q. Dao, B. R. Zeydel, V. Zyuban, V. G. Oklobdžija, "A Method for Energy Optimization of Digital Pipelined Systems", The Fourth Annual IBM Austin Conference on Energy-Efficient Design, ACEED 2005, Austin, Texas, March 1-3, 2005.

4. M. Vratonjic, B. R. Zeydel, H. Q. Dao, V. G. Oklobdzija, "Low-Power Aspects of Different Adder Topologies," 37th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, Nov. 9-12, 2003.

5. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy Minimization Method for Optimal Energy-Delay Extraction," European Solid-State Circuits Conference, Estoril, Portugal, Sept. 16-18, 2003.

6. H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija, "Energy Optimization of High-Performance Circuits," 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, Italy, Sept. 10-12, 2003.

7. B. R. Zeydel, V. G. Oklobdzija, S. Mathew, R. Krishnamurthy, S. Borkar, "A 90nm 1GHz 22mW 16x16-bit 2's Complement Multiplier for Wireless Baseband", Symposia on VLSI Technology and Circuits, 2003.

8. V. G. Oklobdzija, B. R. Zeydel, H. Dao, S. Mathew, R. Krishnamurthy, "Energy-Delay Estimation of High-Performance Microprocessor VLSI Adders," 16th Symposium on Computer Arithmetic, Santiago de Compostella, Spain, June 15-18, 2003.

9. H. Dao, V. Oklobdzija, "Performance Comparison of VLSI Adders Using Logical Effort," 2002 Workshop on Power and Timing Modeling, Optimization and Simulation, Seville, Spain, Sept. 2002.

10. H. Dao, V. Oklobdzija, "Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders," 35th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, Nov. 4-7, 2001.

11. H. Dao, V. Oklobdzija, "Application of Logical Effort on Delay Analysis of 64-bit Static Carry-Lookahead Adder," 35th Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, California, Nov. 4-7, 2001.