4th IEEE Symposium on Computer Arithmetic
October 25-26, 1978
Santa Monica, California
General Chair: Milos D. Ercegovac
Program Co-Chair: Algirdas Avizienis
Milos D. Ercegovac, Algirdas Avizienis, "The Fourth IEEE Symposium on Computer Arithmetic: Foreword"
D. W. Matula, "Basic Digit Sets for Radix Representation of the Integers"
R. N. Horspool, E. C. R. Hehner, "Exact Arithmetic Using a Variable-Length p-adic Representation"
K. Hwang, T. P. Chang, "An Interleaved Rational/Radix Arithmetic System for High-Precision Computations"
I. Koren, Y. Maliniak, "A Unified Approach to a Class of Number Systems"
D. W. Matula, P. Kornerup, "A Feasibility Analysis of Binary Fixed-Slash and Floating-Slash Number Systems"
P. Kornerup, D. W. Matula, "A Feasibility Analysis of Fixed-Slash Rational Arithemtic"
A. G. Slekys, A. Avizienis, "A Modified Bi-Imaginary Number Systems"
L. A. Liddiard, "Required Scientific Floating Point Arithmetic"
T. E. Hull, "Desirable Floating-Point Arithmetic and Elementary Functions for Numerical Computation"
K. S. Frankowski, "A Realistic Model for Error Estimates in the Evaluation of Elementary Functions"
E. K. Reuter, J. P. Jeter, J. W. Anderson, B. D. Shriver, "Some Experiments Using Interval Arithmetic"
E. V. Krishnamurthy, H. Venkateswaran, "Multivariable Polynomial Processing - Applications to Interpolation"
D. P. Agrawal, "On Arithmetic Inter-relationships and Hardware Interchangeability of Negabinary and Binary Systems"
O. N. Garcia, H. Glass, S. C. Haimes, "An Approximate and Empirical Study of the Distribution of Adder Inputs and Maximum Carry Length Propagation"
D. P. Agrawal, T. R. N. Rao, "On Modular(2n + 1) Arithmetic Logic"
C. Y. Chow, J. E. Robertson, "Logical Design of a Redundant Binary Adder"
A. Weinberger, "Parallel Adders Using Standard PLAs"
D. E. Atkins, S. C. Ong, "A Comparison of Two Approaches to Multi-Operand Binary Addition"
L. Dadda, "Multiple Addition of Binary Serial Numbers"
R. S. Lim, "High-Speed Multiplication and Multiple Summand Addition"
K. G. Tan, "The Theory and Implementation of High-Radix Division"
K. S. Trivedi, J. G. Rusnak, "Higher Radix On-Line Division"
C. Wrathall, T. C. Chen, "Convergence Guarantee and Improvements for a Hardware Exponential and Logarith Evaluation Scheme"
M. D. Ercegovac, "An On-Line Square Rooting Algorithm"
M. D. Ercegovac, M. M. Takata, "An Arithmetic Module for Efficient Evaluation of Functions"
F. A. Schreiber, R. Stefanelli, "Two Methods for Fast Integer Binary-BCD Conversion"
A. Svoboda, "Arithmetic Circuit Fault Detection by Modular Encoding"
G. A. Jullien, W. C. Miller, "Application of the Residue Number System to Computer Processing of Digital Signals"
D. Cohen, "Mathematical Approach to Iterative Computation Networks"
E. E. Swartzlander, Jr, "Merged Arithmetic for Signal Processing"
D. D. Gajski, L. P. Rubinfield "Design of Arithmetic Elements for Burroughs Scientific Processor"
S. Waser, "Survey of Arithmetic Integrated Circuits"
S. L. Lillevik, P. D. Fisher, "Computational Design Alternatives with Microprocessor-Based Systems"