7^th IEEE Symposium on Computer Arithmetic

June 4-6, 1985
University of Illinois, Urbana, Illinois

General Chair: Daniel D. Gajski
Program Co-Chair: Ahmed Sameh


[contents]

Preface

K. Hwang, D. D.Gajski and Ahmed Sameh, "The Seventh IEEE Symposium on Computer Arithmetic: Foreword"

Session 1: Efficient Adders and ALU Designs - D. Atkins, Chairman

V. G. Oklobdzija and E. R. Barnes, "Some Optimal Schemes for ALU Implementations in VLSI Technology"

T. -F. Ngai and M. J. Irwin, "Regular, Area-Time Efficient Carry-Lookahead Adders"

H. Kobayashi, "A Multioperand Two's Complement Addition Algorithm"

R. J. Zaccone and J. L. Barlow, "Improved Normalization Results for Digit On-Line Arithmetic"

L. Ciminiera and A. Serra, "Efficient Serial-Parallel Arrays for Multiplication and Addition"

Session 2: Fast Multipliers and Dividers - E. Swartzlander Jr., Chairman

S. P. Smith and H. C. Torng, "Design of a Faster Inner Product Processor"

R. De Mori and R. Cardin, "Design for a Recursive Paralllel Multiplier"

M. D. Ercegovac and T. Lang, "A Division Algorithm with Prediction of Quotient Digits"

L. Dadda, "Fast Multipliers for Two's - Complement Numbers in Serial Form"

G. S. Taylor, "Radix 16 SRT Dividers with Overlapped Quotient Selection Stages"

Session 3: Floating - Point Arithmetic - W. Kahan, Chairman

W. Zadrozny, "Axiomatizations of Floating Point Arithmetics"

M. Ohhashi and R. E. Schneider, "High-Speed Computation of Unary Functions"

T. Gross, "Floating - Point Arithmetic on a Reduced - Instruction - Set Processor"

J. Fandrianto and B. Y. Woo, "VLSI Floating - Point Processors"

J. A. Eldon, "A Family of CMOS Floating Point Arithmetic Chips"

Session 4: Systolic Arithmetic Schemas D. Gajski, Chairman

J. Schaeffer and D. Makarenko, "Systolic Polynomial Evaluation and Matrix Multiplication with Multiple Precision"

R. P. Brent and H. T. Kung, "A Systolic Algorithm for Integer GCD Computation"

H. D. Cheng and K. S. Fu, "Algorithm Partition for a Fixed-Size VLSI Architecture Using Space-Time Domain Expansion"

E. T. Chow and D. I. Moldovan, "Prime Factor DFT Parallel Processor Using Wafer Scale Integration"

Session 5: Panel Discussions on Directions in Computer Arithmetic K. Hwang, Moderator, U. Kulisch, J. Robertson, D. Matula, E. Swartzlander, H. Aiso, B. Woo, M. Ercegovac and L. Dadda, Panelists

Session 6: Elementary Function Evaluation – M. J. Irwin, Chairman

A. Naseem and P. D. Fisher, "The Modified Cordic Algorithm"

T. Kurokawa and H. Aiso, "Polynomial Transformer"

J. Bannur and A. Varma, "The VLSI Implementation of a Square Root Algorithm"

X. Li and L. M. Ni, "A Pipeline Architecture for Computing Cumulative Hypergeometric Distributions"

L. Dadda, "Squarers for Binary Numbers in Serial Form"

Session 7: Rational and Residue Arithmetic – F. J. Taylor, Chairman

C. A. Papachristou, "Multi-Input Residue Arithmetic Utilizing Read-Only Associate Memory"

D. Y. Y. Yun and C. N. Zhang, "Binary Paradigm and Systolic Array Implementation for Residue Arithmetic"

W. E. Ferguson, Jr. and D. W. Matula, "Rationally Biased Arithmetic"

I. S. Reed, T. K. Truong, J. J. Chang, H. M. Shao and I. S. Hsu, "VLSI Residue Multiplier Modulo a Fermat Number"

P. Kornerup and D. W. Matula, "Finite-Precision Lexicographic Continue Fraction Number Systems"

Session 8: Arithmetic in Signal / Image Processing, P. Kornerup, Chairman

K. Taniguchi, "Three Dimentional IC's and Application to High Speed Image Processor"

E. Swartzlander Jr., and J. Eldon, "Arithmetic for High Speed FFT Implementation"

W. Liu, J. C. Duh and D. E. Atkins, "The Design of a Vector-Radix 2DFFT Chip"

V. Cantoni, M. Ferretti, S. Levialdi and R. Stefanelli, "PAPIA: Pyramidal Architecture for Parallel Image Analysis"

F. J. Taylor, "A More Efficient Residue Arithmetic Implementation of the FFT"

Session 9: Large-Scale Scientific Computations, A. Sameh, Chairman

D. Gannon, "On the Structure of Parallelism in a Highly Concurrent PDE Solver"

F. T. Luk, "A Parallel Method for Computing the Generalized Singular Value Decomposition"

K. Hwang and Z. Xu, "Multiprocessors for Evaluating Compound Arithmetic Functions"

J. J. Dongarra and D. C. Sorensen, "A Fast Algorithm for the Symmetric Eigenvalue Problem"

Session 10: Fault Tolerant Arithmetic, I. Reed, Chairman

S. Kaushik, "Multiple Error Correction and Addictive Overflow Detection with Magnitude Indices in Residue Code"

A. Avizienis, "Arithmetic Algorithms for Operands Encoded in Two-Dimensional Low-Cost  Arithmetic Error Code"

T. R. N. Rao and K. Vathanvit, "A Class of A(N + C) Codes and Its Properties"

T. C. Chen, "Maximal Redundancy Signed-Digit Systems"

Session 11: New Arithmetic Systems – H. Garner, Chairman

S. M. Rump, "Higher Order Computer Arithmetic"

D. M. Chiarulli, W. G. Rudd and D. A. Buell, "DRAFT: A Dynamically Reconfigurable Processor for Integer Arithmetic"

J. H. Bleher, A. E. Roeder and S. M. Rump, "ACRITH: High-Accuracy Arithmetic – An Advanced Tool for Numerical Computation"

W. Kahan and E. LeBlanc, "Anomalies in the IBM ACRITH Package"

R. Lohner, J. Wolff V. Gudenberg, "Complex Interval Division with Maximum Accuracy"